Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word In Frame) - Motorola DSP56309 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data Out
Flags

Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)

7.4.2.13 Enabling, Disabling ESSI Data Transmission
The ESSI has three transmit enable bits (TE[2:0]), one for each data transmitter. The
process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in
asynchronous mode. The normal transmit enable sequence is to write data to one or
more transmit data registers (or the time slot register (TSR)) before setting the TE bit. The
normal transmit disable sequence is to clear the TE, transmit interrupt enable (TIE), and
transmit exception interrupt enable (TEIE) bits after the transmit data empty (TDE) bit is
set. In network mode, clearing the appropriate TE bit and setting it again disables the
corresponding transmitter (0, 1, or 2) after transmission of the current data word. The
transmitter remains disabled until the beginning of the next frame. During that time
period, the corresponding SC (or STD in the case of TX0) signal remains in the
high-impedance state.
7.4.2.14 CRB ESSI Transmit 2 Enable (TE2) Bit 14
The TE2 bit enables the transfer of data from TX2 to transmit shift register 2. TE2 is
functional only when the ESSI is in synchronous mode and is ignored when the ESSI is
in asynchronous mode.
When TE2 is set and a frame sync is detected, transmitter 2 is enabled for that frame.
When TE2 is cleared, transmitter 2 is disabled after completing transmission of data
currently in the ESSI transmit shift register. Any data present in TX2 is not transmitted. If
TE2 is cleared, data can be written to TX2; the TDE bit is cleared, but data is not
transferred to transmit shift register 2.
7-22
Slot 0
DSP56309UM/D
Wait
MOTOROLA
Slot 0
AA0684