Figure 4-2 Parallel Port B Registers - Motorola DSP56012 User Manual

Parallel Host Interface
Port B Configuration
23
0 0 0 0 0
X:$FFEC
BC1
23
X:$FFED 0 0 0 0 0
23
X:$FFEE
0 0 0 0 0
4-4
0 0 0 0 0 0
BC0
0 0 Parallel I/O (Reset Condition)
0 1 HI
1 0 HI (with HACK pin as GPIO)
1 1 Reserved
BD BD BD
0 0 0 0
14 13 12
BDx
0 Input (Reset Condition)
1 Output
PB PB PB
0 0 0 0
14 13 12

Figure 4-2 Parallel Port B Registers

DSP56012 User's Manual
0 0 0 0 0 0 0
Function
BD BD BD BD BD BD
11 10 9 8 7 6
Data Direction
PB PB PB PB PB PB
11 10 9 8 7 6
0
Port B Control
BC BC
Register
0 0 0 0
1 0
(PBC)
0
Port B Data
Direction
BD BD BD BD BD BD
Register
5 4 3 2 1 0
(PBDDR)
0
Port B Data
PB PB PB PB PB PB
Register
5 4 3 2 1 0
(PBD)
AA0308.11
MOTOROLA