Main Pll Powerdown Register (Mainpll_Pwd); Main Pll Powerdown Register (Mainpll_Pwd) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Control Module

1.16.1.2.2 Main PLL Powerdown Register (MAINPLL_PWD)

The MAINPLL_PWD register is used to power down the individual output clocks of the main PLL.
The Main PLL Powerdown Register (MAINPLL_PWD) is shown in
Table 1-157.
31
7 6
PWD_CLK7 PWD_CLK6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-157. Main PLL Powerdown Register (MAINPLL_PWD) Field Descriptions
Bit Field
31-8 Reserved
7 PWD_CLK7
6 PWD_CLK6
5 PWD_CLK5
4 PWD_CLK4
3 Reserved
2 PWD_CLK2
1 PWD_CLK1
0 Reserved
276
Chip Level Resources
Preliminary
Figure 1-117. Main PLL Powerdown Register (MAINPLL_PWD)
5 4
PWD_CLK5 PWD_CLK4
R/W-0 R/W-0
Value Description
0 Reserved. Read returns 0.
1-0 Main PLL Clock7 Powerdown. Setting this bit powers down clock 7 (Audio PLL Reference
clock).
1-0 Main PLL Clock6 Powerdown. Setting this bit powers down clock 6 (USB Reference clock).
1-0 Main PLL Clock5 Powerdown. Setting this bit powers down clock 5 (SYSCLK24).
1-0 Main PLL Clock4 Powerdown. Setting this bit powers down clock 4 (SYSCLK4).
0 Reserved
1-0 Main PLL Clock2 Powerdown. Setting this bit powers down clock 2 (SYSCLK2).
1-0 Main PLL Clock1 Powerdown. Setting this bit powers down clock 1 (SYSCLK1).
0 Reserved. Read returns 0.
© 2011, Texas Instruments Incorporated
Figure 1-117
Reserved
R-0
3 2
Reserved PWD_CLK2
R/W-0 R/W-0
www.ti.com
and described in
8
1 0
PWD_CLK1 Reserved
R/W-0 R-0
SPRUGX9 – 15 April 2011
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