Control Module
1.16.1.3.5 TPTC Configuration Register (TPTC_CFG)
The TPTC_CFG register configures the default burst size for TPTC0, 1, 2, and 3.
The TPTC Configuration Register (TPTC_CFG) is shown in
31
7
6
TC3DBS
R/W-11
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-202. TPTC Configuration Register (TPTC_CFG) Field Descriptions
Bit
Field
31-8
Reserved
7-6
TC3DBS
5-4
TC2DBS
3-2
TC1DBS
1-0
TC0DBS
304
Chip Level Resources
Preliminary
Figure 1-161. TPTC Configuration Register (TPTC_CFG)
Reserved
R-0
5
4
TC2DBS
R/W-11
Value
Description
0
Reserved. Read returns 0.
TC3 Default Burst Size
0
16 byte
01
32 byte
10
64 byte
11
128 byte
0-3h
TC2 Default Burst Size.
0-3h
TC1 Default Burst Size.
0-3h
TC0 Default Burst Size.
© 2011, Texas Instruments Incorporated
Figure 1-161
and described in
3
2
TC1DBS
R/W-11
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Table
1-202.
8
1
0
TC0DBS
R/W-11
SPRUGX9 – 15 April 2011
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