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LSI S pecification
7.28. Data Bridge Transmit/Receive Status Register [A]
Data bridge transmit/receive status register indicates status of packet to be transmitted/received by bridge-Ach.
Bit
Bit
AD
R/W
15
14
Tx
Rx
4Eh
R
busy-
busy-
A
A
Initial Value
'0'
'0'
BIT
Bit Name
15
Tx busy-A
14
Rx busy-A
13
Rx 1STP-A
Rx EMI
12
chg-A
11
Rx o/e chg-A
Rev.1.0
Bit
Bit
Bit
Bit
13
12
11
10
Rx
Rx
Rx
Rx o/e
1STP-
EMI
dlen
chg-A
A
chg-A
err-A
'0'
'0'
'0'
'0'
Action
Value
Indicates that bridge-Ach is not in the process of transmit.
0
Indicates '0' when Tx end- A (10h-bit14) is set at '1' and transmit process is
stopped.
Read
Indicates that bridge-Ach is in the process of transmit.
1
Indicates '1' when Tx start -A (10h-bit15) is set at '1' and transmit process is
started.
Indicates that bridge-Ach is not in the process of receive.
0
Indicates '0' when Rx end-A (3Ch -bit6) is set at '1' and receive process is stopped.
Read
Indicates that bridge-Ach is in the process of receive.
1
Indicates '1' when Rx start-A (3Ch -bit7) is set at '1' and receive process is started.
Indicates that Isochronous packet received after starting receive process is not the
0
first packet received.
Read
Indicates that the first Isochronous packet is received after receive process is
1
started.
Clears to '0' by lead of this register.
Indicates that EMI information of received Isochronous packet header is not
0
changed.
Read
Indicates that EMI informatio n of received Isochronous packet header has changed
1
from just former EMI information of packet received by Isochronous-cycle.
Clears to '0' by lead of this register.
Indicates that odd/even information of received Isochronous packet header is not
0
changed.
Read
Indicates that odd/even information of received Isochronous packet header has
changed from just former odd/even information of packet received by
1
Isochronous-cycle.
Clears to '0' by lead of this register.
Bit
Bit
Bit
Bit
9
8
7
6
Tx
Rx
Rx 56
-
late-A
late-A
err-A
'0'
'0'
'0'
'0'
Function
62
MB86617A
Bit
Bit
Bit
Bit
5
4
3
2
BRG
Rx
BRG
Rx
FIFO
stype
FIFO
DBC
emp-
err-A
full-A
err-A
A
'0'
'0'
'1'
'0'
Fujitsu VLSI
Bit
Bit
1
0
Rx
Rx
CIP
FMT
err-A
err-A
'0'
'0'
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