Chapter 20 Clock Monitor; Functions Of Clock Monitor; Configuration Of Clock Monitor - NEC 78K0/KD1 Series User Manual

20.1 Functions of Clock Monitor

The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal
when the X1 input clock is stopped.
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, refer to CHAPTER 19 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
• In STOP mode and during the oscillation stabilization time
• When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1)
• During the oscillation stabilization time after reset is released
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)

20.2 Configuration of Clock Monitor

Clock monitor consists of the following hardware.
Item
Control register Clock monitor mode register (CLM)
X1 input clock
Ring-OSC clock
360

CHAPTER 20 CLOCK MONITOR

Table 20-1. Configuration of Clock Monitor
Configuration
Figure 20-1. Block Diagram of Clock Monitor
Enable/disable
Clock monitor mode register (CLM)
Preliminary User's Manual U16315EJ1V0UD
Internal reset signal
CLME