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21.1 Functions of Clock Monitor
The clock monitor samples the high-speed system clock using the on-chip Ring-OSC, and generates an internal
reset signal when the high-speed system clock is stopped.
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, see CHAPTER 20 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
stabilization time
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
21.2 Configuration of Clock Monitor
The clock monitor includes the following hardware.
Item
Control register
Clock monitor mode register (CLM)
High-speed system clock oscillation
control signal (MCC, MSTOP)
High-speed system clock oscillation
stabilization status (OSTC overflow)
Remark MCC:
Bit 7 of the processor clock control register (PCC)
MSTOP: Bit 7 of the main OSC control register (MOC)
OSTC:
Oscillation stabilization time counter status register (OSTC)
CHAPTER 21 CLOCK MONITOR
Table 21-1. Configuration of Clock Monitor
Configuration
Figure 21-1. Block Diagram of Clock Monitor
Internal bus
Clock monitor
mode register (CLM)
CLME
Operation mode
controller
High-speed system clock
Ring-OSC clock
User's Manual U16899EJ2V0UD
High-speed system
Internal reset
clock oscillation
signal
monitor circuit
397
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