Interrupt Response Time - NEC V850E/IA1 mPD703116 User Manual

(2) Generation of exception in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
...
• TRAP instruction
...
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt
request (0 is the highest priority), but it can be set as desired via software. Setting of the priority order level
is done using the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxlCn), which is provided
for each maskable interrupt request. After system reset, an interrupt request is masked by the xxMKn bit
and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits.
The priority order of maskable interrupts is as follows.
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the
servicing of the higher priority interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt servicing has been completed and
the RETI instruction has been executed.
Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed),
maskable interrupts are suspended and not acknowledged.

7.7 Interrupt Response Time

The following table describes the V850E/IA1 interrupt response time (from interrupt generation to start of interrupt
servicing).
202
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User's Manual U14492EJ3V0UD
← Exception such as TRAP instruction acknowledged.
(Low)