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6.13 Boundary of Memory Area
The transfer operation is not guaranteed if the source or the destination address is over the area of DMA objects
(external memory, internal RAM, external I/O, or internal peripheral I/O) during DMA transfer.
6.14 Transfer of Misalign Data
16-bit DMA transfer of misalign data is not supported. If the source or the destination address is set to an odd
address, the LSB bit of the address is forcibly accepted as "0".
6.15 Clocks of DMA Transfer
Table 6-3 lists the overhead before and after DMA transfer and minimum execution clock for DMA transfer.
From accepting DMARQn to falling edge of DMAAKn
External memory access
Internal RAM access
Internal peripheral I/O access
From rising edge of DMAAKn to falling edge of TCn
Remark n = 0 to 3
6.16 Maximum Response Time to DMA Request
Under the conditions shown below, the response time to a DMA request becomes the maximum time (this is the
state permitted by the DRAM refresh cycle).
(1) Condition 1
Condition
Response time
D0 to D15 (input/output)
194
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
Table 6-3. Minimum Execution Clock in DMA Cycle
Instruction fetch from external memory at the 8-bit data bus width
Tinst × 4 + Tref
DMARQn (input)
DMAAKn (output)
Fetch (1/4) Fetch (2/4) Fetch (3/4) Fetch (4/4)
User's Manual U12688EJ4V0UM00
4 clocks
Refer to miscellaneous memory and I/O cycle
2 clocks
3 clocks
1 clock
Refresh
DMA cycle
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