DDC Total-AceXtreme MIL-STD-1553 Design Manual page 62

If the host then initiates a memory write transfer, the last register write command will
be drained from the FIFO at approximately the same time that the host writes its 32
word. This is the marginal case. If the memory write burst began with 15 or fewer
register write words in the command FIFO, then the FIFO will not fill, and the Total-
AceXtreme® will not assert its CPU_nSTOP output. In this case, the Total-
AceXtreme will assert its nDATA_RDY output because the written word(s) has
(have) been pushed on to the FIFO, even though the word(s) haven't yet been
transferred to Total-AceXtreme memory.
However, if the memory write burst began with 17 or more register write words
already in the FIFO, then the FIFO will fill to capacity and the Total-AceXtreme's
CPU_nSTOP output will be asserted (with nDATA_RDY de-asserted high), thereby
terminating the memory write transfer.
Another case is the host performing a read transfer (even a single word read) when
the command FIFO is partially full. In this case, unless the host performs a multi-word
burst read transfer that overflows the command FIFO, the Total-AceXtreme will not
assert its CPU_nSTOP output. However, in this case, the read transfer will not
complete until all of the register write requests are first drained from the FIFO. For
example, if the FIFO size is 32 words, there are 16 register write words on the FIFO,
and the host performs a single-word memory read transfer, then there will be a delay
of slightly over 400 ns (16 • 25 ns) before the Total-AceXtreme asserts its
nDATA_RDY output low. The worst case additional wait time prior to nDATA_RDY
asserting low for a read transfer would occur for a situation where there are 31
register write operations already queued up in the command FIFO ahead of the read
command. In this situation, the additional delay time would be = (31 • 25 ns) = 775
ns.
6.4.3 Rules for Synchronous Burst Mode Transfers
The following rules must be adhered to when performing Synchronous burst mode
transfers:
• There is no Asynchronous burst mode, only a Synchronous burst mode.
• To initiate a non-multiplexed burst transfer, both nSELECT and
nDATA_STRB must be asserted low on the same host clock cycle.
• The following rules are applicable specifically for the multiplexed
Synchronous mode:
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In multiplexed mode, the Total-AceXtreme supports only sequential
bursts. In multiplexed mode, random busts are not supported.
nSELECT must be asserted during the same host clock cycle or prior to
ADDR_LAT asserting high.
H O S T I N T E R F A C E
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