DDC Total-AceXtreme MIL-STD-1553 Design Manual page 120

Signal Name BALL
PCI_AD(04) (I/O)
PCI_AD(03) (I/O)
PCI_AD(02) (I/O)
PCI_AD(01) (I/O)
PCI_AD(00) (I/O) LSB
GNT# (I)
REQ# (O)
PERR# (I/O)
IDSEL (I)
DEVSEL# (I/O)
STOP# (I/O)
IRDY# (I/O)
TRDY# (I/O)
FRAME# (I/O)
PAR (I/O)
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Table 18. PCI Signals
Pullup/
Pulldown
K3 None
M5 None
L4 None
K4 None
L5 None
A6 None Grant indicates to the agent that access to the bus has been granted. This is
a point-to-point signal. Every master has its own GNT# which must be
ignored while RST# is asserted.
B7 None Request indicates to the arbiter that the Total-AceXtreme desires use of the
bus. This is a point-to-point signal. Every master has its own REQ# output
which must be tri-stated while RST# is asserted.
G2 None Parity Error. This pin is used for reporting parity errors during the data portion
of the bus transaction for all cycles except a Special Cycle. It is sourced by
the agent receiving data and driven active two clocks following the detection
of an error. This signal is driven inactive (high) two clocks prior to returning to
the tri-state condition.
D2 None Initialization Device Select. This pin is used as a chip select during
configuration read or write operations.
J1 None Device Select. This signal is sourced by an active target upon decoding that
its address and bus commands are valid. For bus masters, it indicates
whether any device has decoded the current bus cycle.
H2 None Stop. The Stop signal is sourced by the selected target and conveys a
request to the bus master to stop the current transaction.
C3 None Initiator Ready. This signal is sourced by the bus master and indicates that
the bus master is able to complete the current data phase of a bus
transaction. For write operations, it indicates that valid data is on the
PCI_AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are
asserted together.
J3 None Target Ready. This signal is sourced by the selected target and indicates that
the target is able to complete the current data phase of a bus transaction. For
read operations, it indicates that the target is providing valid data on the
PCI_AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are
asserted together.
H3 None Frame. This signal is driven by the current bus master and identifies both the
beginning and duration of a bus operation. When FRAME# is first asserted, it
indicates that a bus transaction is beginning and that valid addresses and a
corresponding bus command are present on the PCI_AD[31:0] and
C/BE[3:0]# lines, qualified by HOST_CLOCK. When FRAME# is de-asserted
the transaction is in the final data phase or has been completed.
L2 None Parity. This signal is even parity across the entire PCI_AD[31:0] field along
with the C/BE[3:0]# field. The parity is stable in the clock following the
address phase and is sourced by the Bus Master. During the data phase for
write operations, the Bus Master sources this signal on the clock following
IRDY# active. During the data phase for read operations, this signal is
sourced by the Target and is valid on the clock following TRDY# active. The
PAR signal therefore has the same timing as PCI_AD[31:0], delayed by one
clock.
T O T A L - A C E X T R E M E ® S I G N A L S
Description
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