DDC Total-AceXtreme MIL-STD-1553 Design Manual page 38

For 32-bit mode, individual data transfers may be performed over either
CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). For each transfer,
the host must designate whether or not data will be transferred over the upper
and/or lower 16 bits. This is done by means of the two CPU_WORD_EN(1:0)
inputs to the Total-AceXtreme®.
For read transfers, the Total-AceXtreme indicates when valid data appears on
CPU_DATA(31:0) or CPU_DATA(15:0) by asserting its nDATA_RDY output low.
For the case of Synchronous burst memory read transfers, the first data word will
be driven on to CPU_DATA(31:0) or CPU_DATA(15:0) during the first host clock
cycle when nDATA_RDY is initially asserted low. On each successive host clock
cycle until the end of the burst transfer, a new data word will be driven on to
CPU_DATA(31:0) or CPU_DATA(15:0), while nDATA_RDY remains low.
For Asynchronous write transfers, CPU_DATA(31:0), CPU_DATA(31:16), or
CPU_DATA(15:0) must be presented valid by the host prior to the falling edge of
nDATA_STRB and remain asserted through the full transfer cycle.
For single-word Synchronous write transfers, CPU_DATA(31:0),
CPU_DATA(31:16), or CPU_DATA(15:0) must be presented valid during the
same host clock cycle that nDATA_STRB is asserted low.
For Synchronous burst write transfers, the first data word must be presented on
CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) during the same
host clock cycle that nDATA_STRB is asserted low (or, for the case of a random
write burst, first asserted low). After the Total-AceXtreme asserts its
nDATA_RDY output low, the host must present a new data word on
CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) for each successive
host clock cycle through the end of the burst transfer.
6.2.2.2 Input Signals
• CPU_ADDR(15:0):
16-bit host address bus input. For non-multiplexed Asynchronous transfers,
CPU_ADDR(15:0) must be presented valid by the host prior to the falling edge of
nSELECT and nDATA_STRB and remain asserted through the full transfer cycle.
For non-multiplexed single-word Synchronous transfers, CPU_ADDR(15:0) must
first be presented valid during the same host clock cycle that nDATA_STRB is
asserted low and remain low through the full transfer cycle. For non-multiplexed
sequential Synchronous burst transfers, CPU_ADDR(15:0) must be presented
valid during the same host clock cycle when nDATA_STRB is asserted low.
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