Figure 26. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Memory Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK tWait
HOST_CLK
tCS
nSELECT
tSH
tSS
nDATA_STRB
tAS
CPU_ADDR
tAS
CPU_WORD_EN[1:0]
tAS
MEM_nREG
tAS
MSW_nLSW
tAS
RD_nWR
CPU_DATA
nDATA_RDY
CPU_nSTOP
CPU_nLAST
Figure 26. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Memory Read
Figure 26 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be
asserted for memory accesses, and will remain high.
Data Device Corporation
www.ddc-web.com
tCH
Address
tOH
tDD tOHZ
Data A
tRDD tRDD
Timing
66
H O S T I N T E R F A C E
tWait
tCS
tSH
tSS
tAH
tAH
tAH
tAS tAH
tAH
tDD
Data B
tRDD
tCH tSHC
tOH
tOHZ
tRDD
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