Table of Contents
Advertisement
Table 1. Total-AceXtreme® Series Specifications
PARAMETER
TRANSMITTER (con't)
I
, I
IH
IL
Signals with Pullups
I
(V
= 3.3V)
IH
IN
I
(V
= 0V)
IL
IN
Signals with Pulldowns
I
(V
= 3.3V)
IH
IN
I
(V
= 0V)
IL
IN
Signals without bias
I
(0 < V
< V
)
IH
IN
CC
I
(0 < V
< V
)
IL
IN
CC
V
OH
V
OL
PCI_ADx/CPU_DATAx, nINT, IRDY#, REQ#, FRAME#, TRDY#,
DEVSEL#, STOP#, PERR#, PAR, CBEx
I
OL
I
OH
JTAG_TDO, CPU_STOP_L, CPU_RDY_L, TXDATA_OUT_x,
TX_INH_OUT_x, USER_OUTPUT_x
I
OL
I
OH
C
(Input Capacitance) All signals except for
I
HOST_CLK/PCI_CLK, CLK_IN, and IDSEL
C
(HOST_CLK and CLK_IN pin capacitance)
CLK
Pin inductance
PCI COMPATIBLE LOGIC (see PCI spec 3.3V signaling
environment)
INTA#, nMSTCLR/RST#, GNT#, IDSEL#, SERR#, and
HOST_CLK/PCI_CLK
V
IH
V
IL
C
(Input Capacitance) all PCI except PCI_CLK/HOST_CLK
I
& IDSEL
C
(Input Capacitance) PCI_CLK/HOST_CLK
I
C
(Input Capacitance) IDSEL
I
Data Device Corporation
www.ddc-web.com
MIN
TYP
-10
37
38
-10
-10
-10
V
– 0.4
DDIO
8
4
5
0.5* V
DDIO
-0.3
5
9
O V E R V I E W
MAX
UNITS
+10
µA
114
µA
97
µA
+10
µA
+10
µA
+10
µA
V
0.4
V
mA
-8
mA
mA
-4
mA
10
pF
12
pF
20
nH
V
+ 0.3
V
DDIO
0.3* V
V
DDIO
10
pF
12
pF
8
pF
DS-BU-67301B-G
1/14
- Quick Links:
- Bus Controller Mode
Hide quick links:
Advertisement
Table of Contents
