DDC Total-AceXtreme MIL-STD-1553 Design Manual page 9

L I S T O F T A B L E S
Table 1. Total-AceXtreme® Series Specifications .....................................................................8
Table 2. Supported JTAG Functions ....................................................................................... 26
Table 3. Total-AceXtreme® Host Interface Configuration Options .......................................... 28
Table 4. Summary of the Operation of the nDATA_RDY Output Signal for Synchronous
Single-Word Memory and Register Accesses ................................................................... 33
Table 5. Asynchronous 16-bit Mode Configuration Options .................................................... 36
Table 6. Asynchronous Transfers ............................................................................................ 41
Table 7. Asynchronous Timing Information ............................................................................. 41
Table 8. Synchronous 16-bit Mode Configuration Options ...................................................... 55
Table 9. Single-Word Synchronous Transfers ......................................................................... 60
Table 10. Synchronous Burst Transfers .................................................................................. 60
Table 11. Synchronous Timing Parameters............................................................................. 61
Table 12. Total-AceXtreme® PCI Interface Characteristics ..................................................... 88
Table 13. PCI Bus Interface Signals ........................................................................................ 91
Table 14. PCI Timing Information ............................................................................................ 92
Table 15. Protocol Configuration ........................................................................................... 108
Table 16. JTAG Test ............................................................................................................. 109
Table 17. General Purpose Discrete I/O ................................................................................ 109
Table 18. PCI Signals ............................................................................................................ 110
Table 19. CPU Data Bus ....................................................................................................... 112
Table 20. RT Address Signals ............................................................................................... 117
Table 21. Miscellaneous Signals ........................................................................................... 117
Table 22. Additional Connections & Interface to External Transceiver .................................. 120
Table 23. MIL-STD-1553 Interface ........................................................................................ 122
Table 24. Power and Ground Connections ............................................................................ 122
Table 25. No User Connections ............................................................................................. 123
Table 26. Signal Pinout by Ball Location ............................................................................... 124
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