Figure 31. Synchronous, Multiplexed Address 32-Bit - Single-Word Register Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
nDATA_STRB
tALS
ADDR_LAT
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tAS
Address
CPU_DATA
nDATA_RDY
CPU_nSTOP
CPU_nLAST
Figure 31. Synchronous, Multiplexed Address 32-bit - Single-Word Register Read
Figure 31 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For register accesses, the value of the CPU_WORD_EN[1:0] inputs must be
'11'.
3. For a register read access, CPU_nSTOP asserts (low) simultaneous with
nDATA_RDY, and de-asserts (high) on the host clock cycle following
nSELECT returning high.
Data Device Corporation
www.ddc-web.com
tWait
tSH
tSS
tALH
tAH
tAH
tAH
tAH
tDD
Data
tRDD
tSTPD
Timing
71
H O S T I N T E R F A C E
tCH tSHC
tOH
tOHZ
tRDD
tSTPD
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