DDC Total-AceXtreme MIL-STD-1553 Design Manual page 63

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• A burst write transfer may be either sequential or random. If
CPU_STROBE_L is high during the Data Phase, this will cause the burst to
be sequential. In this case, the host does not need to continue to present
its address on to CPU_ADDR(15:0). If nDATA_STRB remains asserted low
during the full data phase, then this will result in a random burst transfer.
For a random burst, the host must provide a new value of its address on to
CPU_ADDR(15:0) for each word to be transferred.
• The Total-AceXtreme does not support either sequential or random
Synchronous register burst read operations.
• A burst read is always a sequential burst read, and is therefore read from
consecutive addresses. The address sampled during the address phase is
used as the first address read. The Total-AceXtreme does not support
random burst reads.
• When the CPU_nLAST input signal is asserted low, this indicates to the
Total-AceXtreme that the last word is being read or written on the
upcoming host clock cycle.
• The actual burst data transfer from or to the Total-AceXtreme begins on
the first host clock when nDATA_RDY is initially asserted low. Data is
transferred on every subsequent cycle until and including the cycle when
the host CPU asserts CPU_nLAST low. In the case of a random burst
transfer, the host must also present a new address on CPU_ADDR(15:0)
for each word to be written.
6.4.4 Synchronous 16-bit Mode Options
In the Synchronous 16-bit mode, the polarity of the MSW_nLSW input is determined
by the value of the POL_SEL static input signal, as shown in Table 8. Note that in the
16-bit Synchronous mode, the low word is always transferred first. Note that
TRIG_SEL has no effect in Synchronous mode and should be tied to logic '1'.
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ADDR_LAT must be assert for one host clock cycle to cause the Total-
AceXtreme® to latch the host address bus from CPU_DATA(15:0).
The falling edge of nDATA_STRB must occur at least one cycle after
ADDR_LAT pulses high.
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