Figure 43. Synchronous, Multiplexed Address - 32-Bit Sequential Burst Memory Read Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

HOST_CLK
nSELECT
nDATA_STRB
tALS
ADDR_LAT
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
CPU_nLAST
tAS
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 43. Synchronous, Multiplexed Address - 32-bit Sequential Burst Memory Read
Figure 43 Notes:
1. With nSELECT asserted low and valid address presented on CPU_DATA, a
positive pulse on the ADDR_LAT input satisfying t
Total-AceXtreme® latching the starting address for the sequential burst. One
host clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low)
while nSELECT remains asserted (low) initiates the sequential burst transfer.
nSELECT must be asserted low through the remainder of the burst cycle. The
nDATA_RDY output is initially asserted low on the same host clock cycle
when the Total-AceXtreme drives the first valid data word on the data bus.
CPU_nLAST must be asserted high until the last word is to be read. On the
rising host clock edge following CPU_nLAST asserting low, the last word is
removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted
(high). At this time (or later) nSELECT must be de-asserted high, completing
the burst read transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory word(s) are valid for this transfer. If either or both these bits is '0',
then the corresponding 16-bit word(s) will return a value of '0000'. These
inputs should be tied high if unused.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tCLK tWait
tCS
tSH
tSS
tALH
tAH
tLS
tAH
Address
Transfer Timing
tDD
Data Data Data Data Data Data
tRDD
ALS
83
H O S T I N T E R F A C E
tCH tSHC
tAH
tAH
tAH
tLS
tLH tLH
tDH
Data Data
tRDD
and T will result in the
AHL
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