Table 20. Rt Address Signals; Table 21. Miscellaneous Signals - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Signal Name BALL
RTAD4 (MSB) (I)
RTAD3 (I)
RTAD2 (I)
RTAD1 (I)
RTAD0 (LSB) (I)
RTADP (I)
RT_AD_LAT (I)
Signal Name BALL
TAG_CLK (I)
TAG_LOAD (I)
TAG_ENABLE (I)
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Table 20. RT Address Signals

Pullup/
Pulldown
H14 50k Pullup RT Address input.
If the RT ADDRESS SOURCE, of the RT_GCFG (RT Global Configuration)
G12 50k Pullup
Register, is programmed to logic "0", then the Total-AceXtreme RT address is
provided by means of these 5 input signals.
G10 50k Pullup
G13 50k Pullup
In addition, if RT ADDRESS SOURCE is logic "0", the source of RT address
G14 50k Pullup
parity is RTADP.
H13 50k Pullup Remote Terminal Address Parity.
This input signal must provide an odd parity sum with RTAD4-RTAD0 in order
for the RT to respond to non-broadcast commands. That is, there must be an
odd number of logic "1"s from among RTAD4-RTAD0 and RTADP.
G11 50k Pullup RT Address Latch.
Input signal used to control the Total-AceXtreme's internal RT address latch.
If RT_AD_LAT is logic "0," then the Total-AceXtreme internal RT Address will
continuously track inputs RTAD4-RTAD0 and RTADP.
When a logic "1" level is applied to the RT_AD_LAT input, the Total-
AceXtreme internal RT address may be optionally latched under software
control.
If RT_AD_LAT transitions from logic '0' to logic "1" while nMSTCLR is high, the
Total-AceXtreme RT address will be latched from inputs RTAD4-RTAD0 and
RTADP on this rising edge.
For single RT mode, to enable the Total-AceXtreme's RT address to be
software programmable, RT_AD_LAT must be connected to logic '1'.

Table 21. Miscellaneous Signals

Pullup/
Pulldown
M13 50k Pullup Time Tag Clock.
External clock that may be used to increment the Time Tag Register. This
option is selected when input ball TAG_ENABLE is logic '1'.
M12 50k Pullup External Time Tag Load Pulse.
Loads 48-bit, Time Tag Counter with value from an internal register
N13 50k Pullup Time Tag Enable.
If this input is set to logic '1', the 48-bit, internal Time Tag counter will be
enabled. A logic '0' input disables the internal Time Tag counter.
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