Figure 40. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Memory Read Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

HOST_CLK
nSELECT
nDATA_STRB
CPU_ADDR
MEM_nREG
RD_nWR
CPU_WORD_EN[1:0]
CPU_nLAST
MSW_nLSW
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 40. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Memory
Figure 40 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) and valid address presented initiates the sequential burst read
transfer. nSELECT must be asserted low through the full burst cycle. The
nDATA_RDY output is initially asserted low on the same clock cycle when the
Total-AceXtreme® drives the first valid 16-bit data word on the data bus.
CPU_nLAST must be asserted high until the last 16-bit word is to be read. On
the rising clock edge following CPU_nLAST asserting low, the last 16-bit word
is removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted
(high). At this time (or later) nSELECT must be de-asserted high, completing
the burst read transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tCLK tWait
tCS
tSH
tSS
tAH
tAS
Address
tAH
tAS
tAS
tAS
tLS
tAS
Read Transfer Timing
H O S T I N T E R F A C E
tAH
tDD
Data Data Data Data Data Data
tRDD
80
tCH tSHC
tAH
tAH
tLS
tLH
tAH
tDH
Data Data
tRDD
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