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DDC Total-AceXtreme MIL-STD-1553 Design Manual

Ultra-small, ultra-low power single package solution
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Total-AceXtreme
Ultra-Small, Ultra-Low Power
MIL-STD-1553 Single Package Solution
Data Sheet
World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package, complete with 1553 protocol,
2 Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package — saves board space and
simplifies 1553 design and layout. Available with development kit to ease integration.
Features
• Small, Fully Integrated 1553 Terminal with
Transformers Inside:
- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a
Single Package
- 324 Ball JEDEC Design Guide 4.5 Standard Size
Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch
• Ultra Low Transceiver Power
• Comprehensive Built-in Self Test
• Versatile User Selectable High-Speed Backend for
PCI or CPU Interface
- Access Time as low as 12.5ns
- DMA Engine with 264MB/sec Burst Transfer Rate
For more information: www.ddc-web.com/BU-67301B
© 2011 Data Device Corporation. All trademarks are the property of their respective owners.
®
• 1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Supports MIL-STD-1553 A/B and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Tx Inhibit Ball for MT Only Applications
- BC Disable Ball for RT Only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 MT Support
• Supports JTAG Boundary Scan
• IRIG-B Input
• 8 Digital Discrete I/O
• Hardware/Software Development Kit with PCI
Evaluation Board and Reference Design Artifacts
Model: BU-67301B

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Summary of Contents for DDC Total-AceXtreme MIL-STD-1553

  • Page 1 - Access Time as low as 12.5ns • Hardware/Software Development Kit with PCI - DMA Engine with 264MB/sec Burst Transfer Rate Evaluation Board and Reference Design Artifacts For more information: www.ddc-web.com/BU-67301B © 2011 Data Device Corporation. All trademarks are the property of their respective owners.
  • Page 2 PMC, PCI, Compact PCI, PC/104, ISA, and VME/VXI. DDC has developed its line of high-speed Fibre Channel and Extended 1553 products to support the real-time processing of field-critical data networking netween sensors, compute notes, data storage displays, and weapons for air, sea, and ground military vehicles.
  • Page 3 Tel: (631) 567-5600, Fax: (631) 567-7358 World Wide Web - http://www.ddc-web.com For Technical Support - 1-800-DDC-5757 ext. 7771 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22...
  • Page 4 Figure 2: Corrected CH. A 1553 Stub designation Rev. F June, 2012 7, 104, 105 Tables 15 – 17: Adjusted column widths Rev. G January, 2014 11, 89 Updated Table 1 and Figure 48 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 5: Table Of Contents

    8.1 Using the Internal Transceivers ................100 8.2 Using External Fiber Optic Transceivers ..............102 THERMAL MANAGEMENT FOR TOTAL-ACEXTREME ........ 104 10 REGISTER AND MEMORY ADDRESSING ............. 107 10.1 Memory Address Space ..................107 10.2 Register Address Space ..................107 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 6 11.1 Signal Descriptions and Pinout by Functional Groups ..........108 11.2 Host Interface Signals ..................... 110 11.3 Pinout Table ......................124 11.4 Total-AceXtreme® Pin Diagram ................128 12 MECHANICAL OUTLINE ................. 129 13 ORDERING INFORMATION ................130 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 7 Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing ..75 Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing ..76 Figure 37. Synchronous, Non-Multiplexed Address, 32-bit - Sequential Burst Memory Read Transfer Timing ......................... 77 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 8 Figure 59. Total-AceXtreme Interface to External McAir Transceiver ........102 Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers ........103 Figure 61. Total-AceXtreme® Pin Diagram ................128 Figure 62. Total-AceXtreme® Mechanical Outline Drawing ..........129 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 9 Table 22. Additional Connections & Interface to External Transceiver ........120 Table 23. MIL-STD-1553 Interface ..................122 Table 24. Power and Ground Connections ................122 Table 25. No User Connections ..................... 123 Table 26. Signal Pinout by Ball Location ................124 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 10: Preface

    This section will define the text formatting used in the rest of the manual Text Usage • BOLD–indicates important information and table, figure, and chapter references. • BOLD ITALIC–designates DDC Part Numbers. • Courier New–indicates code examples. • <…> - indicates user-entered text or commands. Standard Definitions Extended Enhanced Mini-ACE®...

  • Page 11: Technical Support

    1-631-567-5600, ext. 7771 Fax: 1-631-567-5758 to the attention of DATA BUS Applications DDC Website: www.ddc-web.com/ContactUs/TechSupport.aspx Please note that the latest revisions of Software and Documentation are available for download at DDC’s Web Site, www.ddc-web.com. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 12: Overview

    • Asynchronous Access Time 70 ns to read, 40 ns to write • Synchronous Access Time for first word as low as 125 ns to read, 50 ns to write • Synchronous Word Bursts at Host Clock Rate, up to 80 MHz Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 13 Filter Based on RT Address, T/R bit, Sub-Address Advanced Bit Level Error Detection to Isolate Bus Failures • Advanced Data Handler (ADH) For BC, RT, and Multi-RT modes, Option to Combine Control/Status and Data Structures into Consolidated Structures for each Message. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 14 • Thermal Balls for Improved Heatsinking • Leaded and RoHS Versions Available Total-AceXtreme Architectural Reference Guide. This document, which DDC can provide under an NDA, includes detailed information about the Total-AceXtreme architecture. This includes register bit maps and definitions, and detailed information about the AceXtreme’s data structures and operations for BC, Multi-RT, and Monitor...

  • Page 15: Figure 1. Bu-67301B Total-Acextreme

    O V E R V I E W Figure 1. BU-67301B Total-AceXtreme® Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 16: Figure 2. Total-Acextreme® Block Diagram

    O V E R V I E W Figure 2. Total-AceXtreme® Block Diagram Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 17: Specifications

    Output Offset Voltage, Transformer Coupled Across 70 Ω -250 Rise/Fall Time LOGIC All logic inputs, including HOST_CLK/PCI_CLK and CLK_IN + 0.3 DDIO All logic inputs, including HOST_CLK/PCI_CLK and CLK_IN -0.3 Schmidt Hysteresis HOST_CLK/PCI_CLK and CLK_IN Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 18 PCI COMPATIBLE LOGIC (see PCI spec 3.3V signaling environment) INTA#, nMSTCLR/RST#, GNT#, IDSEL#, SERR#, and HOST_CLK/PCI_CLK 0.5* V + 0.3 DDIO DDIO -0.3 0.3* V DDIO (Input Capacitance) all PCI except PCI_CLK/HOST_CLK & IDSEL (Input Capacitance) PCI_CLK/HOST_CLK (Input Capacitance) IDSEL Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 19 • 1553A Compliance 0.01 — -0.01 • 1553B Compliance 0.10 — -0.10 Short Term Tolerance, 1 second — • 1553A Compliance -0.001 0.001 — • 1553B Compliance -0.01 0.01 — Duty Cycle — Jitter Tolerance — Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 20 °C - Protocol — +135 °C Storage Temperature — +150 °C SOLDERING 324-BALL BGA PACKAGE The reflow profile detailed in IPC/JEDEC J-STD-020 is applicable for both the leaded and lead-free versions of Total- AceXtreme. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 21: Additional Support Documents

    AceXtreme device on a PC board and specify the device operational and functional modes. Additional information about MIL-STD-1553, the MIL-STD-1553 core (AceXtreme), and/or internal register/memory information is available, including the following: • The DDC MIL-STD-1553 Designer’s Guide • MIL-STD-1553B Specification • MIL-STD-1553 Handbook Data Device Corporation DS-BU-67301B-G www.ddc-web.com...

  • Page 22: Total-Acextreme® Development Kit

    • AceXtreme Architectural Manual (Contact Factory) Total-AceXtreme® Development Kit DDC offers a Development Kit for the BU-67301 Total-AceXtreme component. This kit contains a PCI Evaluation Card to allow easy integration of the BU-67301 component into a standard desktop personal computer. The Evaluation Card brings...
  • Page 23 • BC Validation Test Report • RT Validation Test Report • Product Brief • Data Sheet • SDK Usage Document • SDK Manual • Evaluation Card Quick Start Guide • Evaluation Card Hardware Manual Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 24: Mil-Std-1553 Modes And Architecture

    Bus Controller Mode The Total-AceXtreme’s MIL-STD-1553 Bus Controller (BC) is based on the 32-bit architecture of DDC’s AceXtreme 1553 Bus Controller. Total-AceXtreme’s BC architecture retains much of the previous generation (Enhanced Mini-ACE, Mini-ACE Mark 3, Micro-ACE (TE), and Total-ACE) 1553 Bus Controller architecture.

  • Page 25: Figure 3. Bus Controller Block Diagram - Remote Terminal Operation

    For RT (and/or Monitor) applications, where the possibility of BC operation must be absolutely prohibited, the Total-AceXtreme includes a DISABLE_BC input signal. In addition to single-RT and Multi-RT operation, the Total-AceXtreme® includes the following capabilities: Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 26 • Flexible Interrupt Conditions, Including 50% and 100% Rollover Interrupts for Circular Buffers • Interrupt Status Queue with Programmable Filtering • Time Tagging Options for Synchronize Mode Codes • Option for RT Auto-Boot with Busy bit Set Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 27: Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation

    Packets. The legacy Monitor modes of operation traditionally implemented in previous generations of DDC MIL-STD-1553 engines can be emulated easily through host software. All information and functionality supported on the legacy Monitor engines is supported on the AceXtreme Monitor engine, or may be extracted from the stored messages.

  • Page 28: Figure 5. Monitor Block Diagram - Advanced Data Handler (Adh)

    For supporting IRIG 106 Chapter 10, the Total-AceXtreme® includes DMA capability, which operates in conjunction with the PCI Initiator interface to transfer monitored data from the 1553 monitor to PCI host space. Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH) Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 29 The ADH also provides the host with indications when its command FIFO (list of messages to transfer) is full or empty. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 30 ADH memory to designated areas in host space or PCI space memory. These transfers may be performed over either the parallel CPU or PCI Target interfaces, or by means of the Total-AceXtreme’s DMA engine and PCI Initiator interface. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 31: Global Features

    The Total-AceXtreme includes a digital IRIG-B input that can be used to synchronize the time tags used by the 1553 interface with external devices. The IRIG-B input will receive and synchronize to a new time-code once per second. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 32: Dma Controller

    Total-AceXtreme System Memory PCI/DMA PCI Bus Local Bus Shared RAM Controller Controller Upstream Downstream Host Memory Figure 6. PCI DMA Block Diagram - Digital I/O Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 33 The power-on default state for DISCRETE_IO_7:0 is as input signals. In addition to DISCRETE_IO_7:0, The Total-AceXtreme includes two user- programmable output-only signals, USER_OUTPUT_2:1. The power-on default state for USER_OUTPUT_2:1 is for logic ‘0’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 34: Built-In Test

    All logic input signals can be sampled and all logic outputs can be selectively driven high, low, or tri-stated as desired by shifting the data through the JTAG port. The Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 35: Table 2. Supported Jtag Functions

    0b000 The EXTEST Instruction allows for a test vector to be applied from the Boundary Scan Register to the external pins of the Total-AceXtreme. Please contact DDC for further information on using the Boundary Scan feature. Data Device Corporation DS-BU-67301B-G www.ddc-web.com...

  • Page 36: Host Interface

    In non-multiplexed mode, the host processor presents its address over the Total- AceXtreme’s address bus input, CPU_ADDR(15:0); that is on a separate path from the data, which is transferred over CPU_DATA(31:0) or CPU_DATA(15:0). In Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 37: Table 3. Total-Acextreme® Host Interface Configuration Options

    CPU interface configuration is used. For the multiplexed address/data modes, the host presents its memory or register address to the Total-AceXtreme on CPU_DATA(15:0) and must assert ADDR_LAT high during this time. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 38 For non-multiplexed sequential Synchronous burst transfers, CPU_ADDR(15:0) must be presented valid during the same host clock cycle when nDATA_STRB is asserted low. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 39 The Total- AceXtreme does not support Synchronous random burst read transfers. In Asynchronous mode, nDATA_STRB must be asserted low through the full data portion of each 32-bit or 16-bit transfer cycle. In Synchronous mode, Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 40 ADDR_LAT input is asserted high. In 32-bit mode, MSW_nLSW is not used and be left unconnected. • CPU_WORD_EN(1:0): These two signals should be active throughout the entire transfer cycle, and operate as follows: Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 41 Asynchronous write transfers, nDATA_RDY asserts low when the Total- AceXtreme has latched data driven by the host over CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). In either case, nDATA_RDY will continue to assert low until the host de-asserts nSELECT high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 42: Table 4. Summary Of The Operation Of The Ndata_Rdy Output Signal For Synchronous Single-Word Memory And Register Accesses

    HOST_CLK rising edge after nSELECT is sampled high. For each of the two transfers for 16-bit Synchronous single-word memory write accesses, nDATA_RDY asserts low for a single host clock cycle when the Total- AceXtreme® internally latches the data transferred over CPU_DATA(15:0). Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 43 Synchronous register (but not memory) read transfer. In either case, CPU_nSTOP will remain low until nSELECT is de-asserted high. For all other correctly completed Synchronous transfers, CPU_nSTOP will remain high. In Asynchronous mode, CPU_nSTOP is not used and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 44: Asynchronous Interface Mode

    In Asynchronous 16-bit mode, the order of data transfers for the upper and lower 16- bit words, along with the polarity of the MSW_nLSW input signal, may be configured by means of the TRIG_SEL and POL_SEL static input signals, as shown in Table 5. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 45: Table 5. Asynchronous 16-Bit Mode Configuration Options

    CPU  RAM 15:0 CPU  RAM 31:16 6.3.1.2 Asynchronous Mode Connection Diagrams Figure 7 through Figure 10 show the four possible Asynchronous mode interface configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and multiplexed. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 46: Figure 7. 32-Bit, Non-Multiplexed Address, Asynchronous Interface

    H O S T I N T E R F A C E Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 47: Figure 8. 32-Bit, Multiplexed Address, Asynchronous Interface

    H O S T I N T E R F A C E Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 48: Figure 9. 16-Bit, Non-Multiplexed Address, Asynchronous Interface

    H O S T I N T E R F A C E Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 49: Figure 10. 16-Bit, Multiplexed Address, Asynchronous Interface

    H O S T I N T E R F A C E Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 50: Table 6. Asynchronous Transfers

    Maximum delay from nDATA_STRB falling edge to nDATA_RDY Wait falling edge (second 16-bit read) Maximum delay from nDATA_STRB falling edge to nDATA_RDY Wait falling edge (write) During READ operations: CPU_DATA valid delay following falling 10pF load Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 51 “Data A” is bits 31:16, and is always transferred prior to the data indicated as “Data B”, which is bits 15:0. For the 16-bit Asynchronous timing diagrams, RD_nWR = ‘1’ to read and ‘0’ to write. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 52: Figure 11. Asynchronous Non-Multiplexed Address 32-Bit Read Timing

    If either or both these bits is ‘0’, then the corresponding 16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 53: Figure 12. Asynchronous Non-Multiplexed Address 32-Bit Write Timing

    If either or both these bits is ‘0’, then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 54: Figure 13. Asynchronous Non-Multiplexed Address 16-Bit Read Timing

    Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 55: Figure 14. Asynchronous Non-Multiplexed Address 16-Bit Write Timing

    In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 56: Figure 15. Asynchronous Multiplexed Address 32-Bit Read Timing

    If either or both these bits is ‘0’, then the corresponding 16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 57: Figure 16. Asynchronous Multiplexed Address 32-Bit Write Timing

    If either or both these bits is ‘0’, then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 58: Figure 17. Asynchronous Multiplexed Address 16-Bit Read Timing

    In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 59: Figure 18. Asynchronous Multiplexed Address 16-Bit Write Timing

    In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 60: Synchronous Host Processor Interface

    32, 16, or 8 words. The default size for the FIFO is 32 words. There is one entry posted in the command FIFO for each 32-bit or 16-bit word to be written to or read from the Total-AceXtreme. This includes the values of the Total- Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 61 Total-AceXtreme asserts nDATA_RDY low, while CPU_nSTOP remains high. In this case, assume a 32-word FIFO that is filled half-way by register write transfers, and a HOST_CLK frequency of 80 MHz. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 62 Synchronous mode: In multiplexed mode, the Total-AceXtreme supports only sequential bursts. In multiplexed mode, random busts are not supported. nSELECT must be asserted during the same host clock cycle or prior to ADDR_LAT asserting high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 63 POL_SEL static input signal, as shown in Table 8. Note that in the 16-bit Synchronous mode, the low word is always transferred first. Note that TRIG_SEL has no effect in Synchronous mode and should be tied to logic ‘1’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 64: Table 8. Synchronous 16-Bit Mode Configuration Options

    CPU  RAM 15:0 CPU  RAM 31:16 6.4.4.1 Synchronous Mode Connection Diagrams Figure 19 through Figure 22 show the four possible Synchronous mode interface configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and multiplexed. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 65: Figure 19. 32-Bit, Non-Multiplexed Address, Synchronous Interface

    H O S T I N T E R F A C E Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 66: Figure 20. 32-Bit, Multiplexed Address, Synchronous Interface

    H O S T I N T E R F A C E Figure 20. 32-bit, Multiplexed Address, Synchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 67: Figure 21. 16-Bit, Non-Multiplexed Address, Synchronous Interface

    H O S T I N T E R F A C E Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 68: Figure 22. 16-Bit, Multiplexed Address, Synchronous Interface

    H O S T I N T E R F A C E Figure 22. 16-bit, Multiplexed Address, Synchronous Interface Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 69: Table 9. Single-Word Synchronous Transfers

    Memory Read Figure 37 Non-Multiplexed Sequential Memory or Write Figure 38 Register Non-Multiplexed Random Memory or Write Figure 39 Register Non-Multiplexed Sequential Memory Read Figure 40 Non-Multiplexed Sequential Memory or Write Figure 41 Register Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 70: Table 11. Synchronous Timing Parameters

    Write cycle latency from nDATA_STRB falling edge to 4•t WAIT- nDATA_RDY falling edge WRITE CPU_DATA valid delay (NOTE) 10pF load nDATA_RDY delay (NOTE) 10pF load CPU_DATA output valid hold time (NOTE) 10pF load CPU_DATA delay to high-Z (NOTE) 10pF load Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 71 ‘0’. For these diagrams, the data indicated as “Data A” is bits 15:0, and is always transferred prior to the data indicated as “Data B”, which is bits 31:16. For the 16-bit Synchronous timing diagrams, RD_nWR = ‘1’ to read and ‘0’ to write. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 72: Figure 23. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Memory Read Timing

    16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be asserted for memory accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 73: Figure 24. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Register Read Timing

    2. For register transfers, the value of the CPU_WORD_EN[1:0] inputs must be ‘11’. 3. For a single-word register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 74: Figure 25. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Write Timing

    These inputs should be tied high if unused. For register transfers, the value of CPU_WORD_EN[1:0] must be ‘11’. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 75: Figure 26. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Memory Read Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be asserted for memory accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 76: Figure 27. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Register Read Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 77: Figure 28. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Memory Write Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 78: Figure 29. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Register Write Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 79: Figure 30. Synchronous, Multiplexed Address 32-Bit - Single-Word Memory Read Timing

    16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 80: Figure 31. Synchronous, Multiplexed Address 32-Bit - Single-Word Register Read Timing

    2. For register accesses, the value of the CPU_WORD_EN[1:0] inputs must be ‘11’. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 81: Figure 32. Synchronous, Multiplexed Address 32-Bit Single-Word Write Timing

    16-bit word(s) will not be written. These inputs should be tied high if unused. For register transfers, the value of CPU_WORD_EN[1:0] must be ‘11’. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 82: Figure 33. Synchronous, Multiplexed Address 16-Bit - Single-Word Memory Read Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 83: Figure 34. Synchronous, Multiplexed Address 16-Bit Single-Word Register Read Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 84: Figure 35. Synchronous, Multiplexed Address 16-Bit Single-Word Memory Write Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 85: Figure 36. Synchronous, Multiplexed Address 16-Bit Single-Word Register Write Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 86: Figure 37. Synchronous, Non-Multiplexed Address, 32-Bit - Sequential Burst Memory Read Transfer Timing

    16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 4. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 87: Figure 38. Synchronous, Non-Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing

    16-bit word(s) will not be written. These inputs should be tied high if unused. For register transfers, the value of CPR_WORD_EN[1:0] must be ‘11’. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 88: Figure 39. Synchronous, Non-Multiplexed Address 32-Bit - Random Burst Write Transfer Timing

    If either or both of these bits is ‘0’, then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 89: Figure 40. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Memory Read Transfer Timing

    (high). At this time (or later) nSELECT must be de-asserted high, completing the burst read transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 90: Figure 41. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 91: Figure 42. Synchronous, Non-Multiplexed Address - 16-Bit Random Burst Write Transfer Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 92: Figure 43. Synchronous, Multiplexed Address - 32-Bit Sequential Burst Memory Read Transfer Timing

    16-bit word(s) will return a value of ‘0000’. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 93: Figure 44. Synchronous, Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing

    16-bit word(s) will not be written to Total-AceXtreme memory. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 94: Figure 45. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Memory Read Transfer Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 95: Figure 46. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing

    2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 96: Figure 47. Timing For Assertion Of Cpu_Nstop - Output During Synchronous Burst Write Transfer

    25 ns each to drain. Therefore, the minimum delay times to prevent a subsequent “STOP” condition are 425 ns for a 32-word command FIFO; 225 ns for a 16-word command FIFO; and 125 ns for an 8-word command FIFO. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 97: Pci Interface

    Total-AceXtreme will never generate a target abort Delayed Transactions Supports up to two simultaneous BAR0/BAR1 Support BAR0 = Total-AceXtreme Memory BAR1 = Total-AceXtreme Registers Zero wait state bursts Supported, for both reads and writes as both Target and Initiator Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 98 • The PCI interface acts as a standard 32-bit PCI device. It can operate at 33 or 66MHz clock rates and will act as a bus master for DMA operations. 6.5.3 PCI Interface Diagram Figure 48 shows the connection between a PCIbus and Total-AceXtreme®. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 99: Figure 48. Interface Between Host Pci Bus And Total-Acextreme® - Pci Signal List

    H O S T I N T E R F A C E Figure 48. Interface Between Host PCI Bus and Total-AceXtreme® - PCI Signal List Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 100: Table 13. Pci Bus Interface Signals

    This signal is used for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. INTA# Interrupt This pin is a level sensitive, active low interrupt to the host. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 101: Table 14. Pci Timing Information

    Target interface will terminate the current transaction by asserting its STOP# output low. Table 14. PCI Timing Information Timing Characteristics DESCRIPTION NOTES UNITS HOST_CLK frequency HOST_CLK cycle time Input setup time input hold time output valid delay 10pF load output high-z delay 10pF load Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 102: Figure 49. Pci Parametric Timing

    DMA transfer HOST_CLK INPUT Input Valid OUTPUT Output Valid Figure 49. PCI Parametric Timing tCLK HOST_CLK FRAME# tWrite Data Address Data Data Data AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Figure 50. PCI Slave Burst Write Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 103: Figure 51. Pci Slave Burst Read - Pci Initiator Timing

    Once the arbiter responds by asserting the Total-AceXtreme’s GNT# input low, the Total-AceXtreme’s PCI Initiator interface will begin its DMA burst write transfer, as shown in Figure 53; or its DMA burst read transfer, as shown in Figure 54. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 104: Figure 52. Pci Dma Start Delay

    Address Data AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Figure 52. PCI DMA Start Delay tCLK HOST_CLK REQ# GNT# FRAME# Address Data Data Data Data AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Figure 53. PCI DMA Burst Write Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 105: Figure 54. Pci Dma Burst Read

    H O S T I N T E R F A C E tCLK HOST_CLK REQ# GNT# FRAME# Address Data Data Data Data AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# Figure 54. PCI DMA Burst Read Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 106: Power Inputs

    1 - 0.1uF Ceramic Chip o 1 - 0.01uF Ceramic Chip In order to minimize power supply noise on the PLL supply pin, DDC recommends the use of a ferrite bead in series with decoupling capacitors as shown in Figure 55.
  • Page 107 160 MHz clock (PLL output) is operational. If this signal does not rise, the internal chip reset will remain in place and the chip will be unresponsive. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 108: Figure 56. Power-Up Initialization Sequence Timing

    P O W E R I N P U T S Figure 56. Power-Up Initialization Sequence Timing Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 109: Mil-Std-1553 Transceiver Options

    Bus Coupler Isolation Transformer 1.0:1.4 1.0:2.038 CHx_1553 Protocol 0.75?Z MIL-STD-1553 Bus Transceiver Logic CHx_1553_L 0.75?Z CHx = CH. A or CH. B CHx_1553-CT Figure 57. Total-AceXtreme® Internal Transceiver and Isolation Transformer Connection to MIL-STD-1553 Bus Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 110: Figure 58. Mandatory Connections For Integrated Transceivers Connection To External Transceivers

    Figure 59 shows the use of Total-AceXtreme for applications requiring compatibility with the McAir standards. For this, DDC’s BU-67401-L0D0L-100 dual 3.3V transceiver includes a McAir-compatible transmitter, while Beta Transformer Technology Corporation’s DSS-3300-1 dual transformer provides both direct and...

  • Page 111: Using External Fiber Optic Transceivers

    Note for this interface, it is necessary to configure the Total-AceXtreme’s Manchester decoders to accept a single-ended input signal. This is done by connecting the nSINGEND to logic ‘0’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 112: Figure 60. Total-Acextreme® Interface To Fiber Optic Transceivers

    M I L - S T D - 1 5 5 3 T R A N S C E I V E R O P T I O N S Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 113: Thermal Management For Total-Acextreme

    MIL-STD-1553 terminals. This is especially true if high transmitter duty cycles are expected. The temperature range specified for DDC's Total-AceXtreme device refers to the case temperature. Any duty cycle is acceptable as long as the case temperature is maintained within the industrial temperature range specified for the –Exx parts.
  • Page 114 ∆T = P *(24.5) = P *(46.9) And: 0.7 = P Which turns into: = 0.7-P and θ in the equation for ∆T, we get: Substituting for P Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 115 This could potentially allow operation at higher ambient temperatures and duty cycles with less expensive heat removal methods. To this end, DDC provides a thermal model that can be use with the FloTherm modeling tool from Mentor Graphics to assign power dissipation numbers...

  • Page 116: Register And Memory Addressing

    When using the CPU interface, the Total-AceXtreme registers are accessed via 32- bit addresses on the CPU bus. Any attempt to read/write a register location beyond address x“3FF” will result in a rollover back to the beginning of the 4Kbyte space. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 117: Total-Acextreme® Signals

    PLL_LOCKED will assert low, and will remain low while nPOR is asserted low. Assuming correct operation of the PLL, PLL_LOCKED will transition from ‘0’ to ‘1’ following a maximum of 100 µs after nPOR goes high. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 118: Table 16. Jtag Test

    Discrete IO bit is independently programmable for input vs. output, and each DISCRETE_IO_4 (I/O) 50k Pullup bit has independent 3-state control. DISCRETE_IO_3 (I/O) 50k Pullup DISCRETE_IO_2 (I/O) 50k Pullup DISCRETE_IO_1 (I/O) 50k Pullup DISCRETE_IO_0 (I/O) 50k Pullup Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 119: 11.2 Host Interface Signals

    None PCI_AD(15) (I/O) None PCI_AD(14) (I/O) None PCI_AD(13) (I/O) None PCI_AD(12) (I/O) None PCI_AD(11) (I/O) None PCI_AD(10) (I/O) None PCI_AD(09) (I/O) None PCI_AD(08) (I/O) None PCI_AD(07) (I/O) None PCI_AD(06) (I/O) None PCI_AD(05) (I/O) None Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 120 IRDY# active. During the data phase for read operations, this signal is sourced by the Target and is valid on the clock following TRDY# active. The PAR signal therefore has the same timing as PCI_AD[31:0], delayed by one clock. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 121: Table 19. Cpu Data Bus

    CPU_DATA[31:16] are only used when the 32-bit mode is enabled. CPU_DATA(27) (I/O) None CPU_DATA(26) (I/O) None For the multiplexed address/data mode, CPU_DATA(15:0) operate as the address bus inputs during the first (address) portion of a transfer cycle. CPU_DATA(25) (I/O) None Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 122 The host CPU accesses Total-AceXtreme registers and internal RAM by means of CPU_ADDR(15:0) CPU_ADDR(11) (I) None CPU_ADDR(10) (I) None In the multiplexed address/data mode for the parallel CPU interface, CPU_ADDR(15:0) may be left unconnected. CPU_ADDR(09) (I) None CPU_ADDR(08) (I) None CPU_ADDR(07) (I) None Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 123 (ADDR_LAT). RD_nWR (I) 50k Pullup Read/Write. Indicating the type of transfer: ‘1’ to read or ‘0’ to write. This signal should be active throughout the entire transfer cycle (See POL_SEL for active high/low options). Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 124 Total-AceXtreme registers are accessed by asserting MEM_nREG = ‘0’. Any attempt to access a register location beyond address x“3FF” will result in a rollover back to the beginning of the 8K register space. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 125 (i.e. a FIFO is full or an invalid transfer). When asserted, the next transfer shall not start until at least one clock after CPU_nSTOP has been de-asserted. CPU_nSTOP is not used in asynchronous mode. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 126: Table 20. Rt Address Signals

    TAG_ENABLE (I) 50k Pullup Time Tag Enable. If this input is set to logic ‘1’, the 48-bit, internal Time Tag counter will be enabled. A logic ‘0’ input disables the internal Time Tag counter. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 127 The clock used for formulating the nINT pulse width will be the Total-AceXtreme’s internal 160 MHz clock for the Asynchronous CPU interface mode, and the HOST_CLK for the Synchronous CPU interface mode. CLOCK_IN (I) None 40 MHz clock input (MIL-STD-1553 bus clock) Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 128 SUBSYSTEM FLAG register bit. In BC, Multi-RT, and Monitor (only) modes, the nSSFLAG input is not used and should be connected to logic ‘1’. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 129: Table 22. Additional Connections & Interface To External Transceiver

    Pulldown should be applied to the respective TX_INH input. Digital transmit inhibit outputs. Connect to TXINH_OUT_A inputs of an external MIL-STD-1553 transceiver. Asserted high to inhibit when not trans- mitting on the respective bus. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 130 “Built-In” RXDATA_OUT_B_L (O) These two signals MUST be separated for transceiver “Transceiverless” operation. operation. Digital Manchester bi-phase receive data inputs. Connect directly to corresponding outputs of a MIL- STD-1553 or MIL-STD-1773 (fiber optic) transceiver. Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 131: Table 23. Mil-Std-1553 Interface

    V15, A11, A12, B11, B12, B13, D11, E10, E14, F10, F13, F14 GND_XCVR P5, P6, P7, P8, P9, Transceiver Ground (V R5, R6, R7, R8, R9, , V10, E11, E12, F11, F12, P11, P12, R11, Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 132: Table 25. No User Connections

    T16, U1, U2, U9, U11, U12, U15, U16, U17, U18, V1, V2, V3, V9, V11, V12, V13, V16, V17, V18, D12, , U3, U4, V4, M8, V5, U5, U8, V8, N10, P10, T10, R10 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 133: 11.3 Pinout Table

    CHB_1553 (I/O) CHA_1553 CHB_1553 (I/O) PCI_AD(16)/CPU_DATA(16) CPU_nSTOP STOP#/CPU_ADDR(08) nINT PCI_AD(27)/CPU_DATA( FRAME#/CPU_ADDR(05) CPU_WORD_EN(0) PCI_AD(28)/CPU_DATA( +3.3V_LOGIC CPU_WORD_EN(1) PCI_AD(29)/CPU_DATA( +3.3V_LOGIC GND_XCVR RST#/nMSTCLR +3.3V_LOGIC GND_XCVR REQ#/CPU_ADDR(12) +3.3V_LOGIC GND_XCVR JTAG_TDO +3.3V_LOGIC GND_XCVR JTAG_nTRST +3.3V_LOGIC GND_XCVR JTAG_TDI TXINH_OUT_A GND_LOGIC TXINH_IN_A GND_XCVR Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 134 +3.3V_LOGIC DISCRETE_IO_5 GND_XCVR DISABLE_BIST DISCRETE_IO_4 nSINGEND DISABLE_BC GND_LOGIC nSSFLAG CHB_1553_L CHB_1553_L PCI_AD(26)/CPU_DATA( PCI_AD(15)/CPU_DATA(15) IDSEL/CPU_ADDR(10) PCI_AD(10)/CPU_DATA(10) nSELECT PCI_AD(24)/CPU_DATA( PCI_AD(04)/CPU_DATA(04) CPU_ADDR(14) GND_LOGIC PCI_AD(01)/CPU_DATA(01) CPU_ADDR(15) GND_LOGIC C/BE[1]#/CPU_ADDR(01) +3.3V_XCVR GND_LOGIC DATA32_n16 +3.3V_XCVR GND_LOGIC POL_SEL +3.3V_XCVR GND_LOGIC RXDATA_OUT_A +3.3V_XCVR Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 135 +1.8V_CORE MSW_nLSW RXDATA_IN_B +1.8V_CORE ADMULTI RXDATA_IN_B_L +1.8V_PLL TRIG_SEL GND_LOGIC TXDATA_OUT_B_L GND_LOGIC TXDATA_OUT_B +3.3V_XCVR GND_XCVR TXINH_OUT_B GND_XCVR nMCRST/nINCMD TEMP_DIODE DISCRETE_IO_3 USER_OUTPUT_2 GND_LOGIC DISCRETE_IO_6 GND_LOGIC CHA_1553_L CHA_1553_L PCI_AD(23)/CPU_DATA( PCI_AD(09)/CPU_DATA(09) HOST_CLK/PCI CLK PCI_AD(14)/CPU_DATA(14) PCI_AD(20)/CPU_DATA( C/BE[0]#/CPU_ADDR(00) GND_LOGIC PCI_AD(05)/CPU_DATA(05) Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 136 Signal Name BALL Signal Name BALL Signal Name +1.8V_CORE PCI_AD(03)/CPU_DATA(03) +1.8V_CORE nDATA_STRB RXDATA_OUT_B +1.8V_CORE +3.3V_LOGIC RXDATA_OUT_B_L +1.8V_CORE GND_LOGIC TXDATA_IN_B_L GND_LOGIC TXDATA_IN_B GND_XCVR GND_XCVR TXINH_IN_B GND_XCVR TAG_LOAD GND_LOGIC TAG_CLK GND_LOGIC DISCRETE_IO_0 GND_LOGIC GND_LOGIC CHA_1553 CHA_1553 Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 137: 11.4 Total-Acextreme® Pin Diagram

    DATA13 DATA9 DATA12 nSTOP R(9) MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM PCI BUS 1553 MISC TEST / PROGRAM PAD XCVR MISC CPU BUS MISC CONFIG PAD (STATIC) Figure 61. Total-AceXtreme® Pin Diagram Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 138: Mechanical Outline

    MECHANICAL OUTLINE Figure 62. Total-AceXtreme® Mechanical Outline Drawing Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...

  • Page 139: Ordering Information

    - CAD Drawing footprints for PADS and Allegro - MTBF Report, BC Validation Report and RT Validation Report - BusTrACEr® with Application Code Generation for Software Development - Drivers for Windows®, Linux®, and VxWorks® Data Device Corporation DS-BU-67301B-G www.ddc-web.com 1/14...
  • Page 140 Data Bus | Synchro/Resolver | Power Controllers | Motor Drives DDC is a leader in the development, design, and manufacture of highly reliable and innovative military data bus solutions. DDC's Data Networking Solutions include MIL-STD-1553, ARINC 429, and Fibre Channel. Each Interface is supported by a complete line of quality MIL-STD-1553 and ARINC 429 commercial, military, and COTS grade cards and components, as well as software that maintain compatibility between product generations.
  • Page 141 FILE NO. 10001296 ASH09 The first choice for more than 50 years—DDC France: DDC Electronique DDC is the world leader in the design and manufacture of high reliability 10 Rue Carle-Herbert data interface products, motion control, and solid-state power controllers 92400 Courbevoie France for aerospace, defense, and industrial automation.

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