Figure 33. Synchronous, Multiplexed Address 16-Bit - Single-Word Memory Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSS
nDATA_STRB
tALH
tALS
ADDR_LAT
tAS
MSB_nLSW
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tAS tAH
MEM_nREG
tAS tAH
Address
CPU_DATA
nDATA_RDY
CPU_nSTOP
CPU_nLAST
Figure 33. Synchronous, Multiplexed Address 16-bit - Single-Word Memory Read
Figure 33 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
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tWait
tCH
tSH
tOH
tDD tOHZ
Data A
tSTPD
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
transfer cycle.
asserted for memory accesses, and will remain high.
tCS
tSH
tSS
tALH
tALS
tAS
tAS tAH
tAS tAH
Address
tSTPD
Timing
73
H O S T I N T E R F A C E
tWait
tCH
tAH
tAH
tAH
tOH
tDD tOHZ
Data B
tRDD tRDD
DS-BU-67301B-G
tSHC
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