Figure 39. Synchronous, Non-Multiplexed Address 32-Bit - Random Burst Write Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
nSELECT
nDATA_STRB
CPU_ADDR
MEM_nREG
RD_nWR
CPU_WORD_EN[1:0]
CPU_nLAST
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 39. Synchronous, Non-Multiplexed Address 32-bit - Random Burst Write
Figure 39 Notes:
1. For a random burst write transfer, both nDATA_STRB and nSELECT must be
asserted low through the entire time of the transfer. The nDATA_RDY output
is initially asserted low on the clock cycle prior to the cycle in which the Total-
AceXtreme® reads the first data word from the data bus. CPU_nLAST must
be asserted high until the last word is to be written. On the rising clock edge
following CPU_nLAST asserting low, the Total-AceXtreme reads the last
word from the data bus, and nDATA_RDY is de-asserted (high). At this time
(or later) nDATA_STRB and nSELECT must be de-asserted high, completing
the burst write transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which bit data memory
word(s) are to be written. If either or both of these bits is '0', then the
corresponding 16-bit word(s) will not be written. These inputs should be tied
high if unused.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tCS
tSS
tAS
Address
tAS
tAS
tLS
tDS
Data
tRDD
Transfer Timing
tAH
Address Address Address Address Address
tDH
Data Data Data Data Data
79
H O S T I N T E R F A C E
tCH tSHC
tSH
tAH
Address Address Address
tAH
tAH
tAH
tLS
tLH tLH
tDH
Data Data Data
tRDD
DS-BU-67301B-G
1/14