DDC Total-AceXtreme MIL-STD-1553 Design Manual page 135

BALL Signal Name
D9 GND_LOGIC
D10 +3.3V_LOGIC
D11 GND_LOGIC
D12 NC
D13 nRTBOOT
D14 DISABLE_MULTI_RT
D15 NC
D16 NC
D17 CHA_1553_L
D18 CHA_1553_L
E1 C/BE[3]#/CPU_ADDR(03)
PCI_AD(22)/CPU_DATA(
E2 22)
PCI_AD(21)/CPU_DATA(
E3 21)
E4 GND_LOGIC
E5 +1.8V_CORE
E6 +1.8V_CORE
E7 +1.8V_CORE
E8 +1.8V_PLL
E9 GND_LOGIC
E10 GND_LOGIC
E11 GND_XCVR
E12 GND_XCVR
E13 TEMP_DIODE
E14 GND_LOGIC
E15 NC
E16 NC
E17 CHA_1553_L
E18 CHA_1553_L
PCI_AD(23)/CPU_DATA(
F1 23)
F2 HOST_CLK/PCI CLK
PCI_AD(20)/CPU_DATA(
F3 20)
F4 GND_LOGIC
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T O T A L - A C E X T R E M E ® S I G N A L S
Table 26. Signal Pinout by Ball Location
BALL Signal Name
K9 RXDATA_OUT_A_L
K10 TXDATA_IN_A
K11 TXDATA_IN_A_L
K12 DISCRETE_IO_2
K13 DISCRETE_IO_1
K14 GND_LOGIC
K15 NC
K16 NC
K17 NC
K18 NC
L1 PCI_AD(13)/CPU_DATA(13)
L2 PAR/CPU_ADDR(04)
L3 PCI_AD(11)/CPU_DATA(11)
L4 PCI_AD(02)/CPU_DATA(02)
L5 PCI_AD(00)/CPU_DATA(00)
L6 MSW_nLSW
L7 ADMULTI
L8 TRIG_SEL
L9 TXDATA_OUT_B_L
L10 TXDATA_OUT_B
L11 TXINH_OUT_B
L12 nMCRST/nINCMD
L13 DISCRETE_IO_3
L14 DISCRETE_IO_6
L15 NC
L16 NC
L17 NC
L18 NC
M1 PCI_AD(09)/CPU_DATA(09)
M2 PCI_AD(14)/CPU_DATA(14)
M3 C/BE[0]#/CPU_ADDR(00)
M4 PCI_AD(05)/CPU_DATA(05)
126
BALL Signal Name
T9 +3.3V_XCVR
T10 NC
T11 EXT_TRIG
T12 NC
T13 USER_OUTPUT_1
T14 NC
T15 NC
T16 NC
T17 CHB_1553_L
T18 CHB_1553_L
U1 NC
U2 NC
U3 NC
U4 NC
U5 NC
U6 RXDATA_IN_B
U7 RXDATA_IN_B_L
U8 NC
U9 NC
U10 +3.3V_XCVR
U11 NC
U12 NC
U13 USER_OUTPUT_2
U14 GND_LOGIC
U15 NC
U16 NC
U17 NC
U18 NC
V1 NC
V2 NC
V3 NC
V4 NC
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