Figure 29. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Register Write Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSH
tSS
nDATA_STRB
tAS
CPU_ADDR
tAS
CPU_WORD_EN[1:0]
tAS
MEM_nREG
tAS
MSW_nLSW
tAS
RD_nWR
tDS
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 29. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Register Write
Figure 29 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for write accesses, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tCH
tDH
Data A
tRDD
tCS
tSH
tSS
Address
tAS
tDS
tRDD
Timing
69
H O S T I N T E R F A C E
tWait
tCH
tAH
tAH
tAH
tAH
tAH
tDH
Data B
tRDD tRDD
DS-BU-67301B-G
tSHC
1/14