DDC Total-AceXtreme MIL-STD-1553 Design Manual page 14

- Options for Transferring based on transmit and/or received messages.
- Transfer control/status structures and/or data words.
- For RT, can filter based on RT Address/T-R bit/Subaddress.
- Filter on Valid and/or Invalid Messages.
- Host Interrupts Based on Time, Number of Messages, or Number of Words.
- Can work in Conjunction with DMA Controller and PCI Initiator Interface.
• Autonomous Built-In Self-Test
- Host Initiated Protocol & RAM Self-Test
- Automatic Power On Self-Test
- Online Loopback Test
- Capability for Channel A-to-B Wraparound Test
- Capability to Test Transmitter Timeout Function
• Provides JTAG Boundary Scan
• IRIG-B Input
• 8 Digital Discrete I/O
• High-Level C Software Development Kits with Drivers for Windows®, Linux®, and
VxWorks®
• Optional Hardware/Software Development Kit with PCI Evaluation Board and
Design Artifacts (see section 2.4)
- PCI Evaluation Board with Cable
- 1 Total-AceXtreme® Component
- BusTrACEr® with Application Code Generation for Software Development
- Drivers for Windows
- Thermal Model, IBIS Model and Schematic Symbols
- PCI Card Reference Design Schematic
• Extended Industrial Temperature Range, -40°C to +100°C
• Thermal Balls for Improved Heatsinking
• Leaded and RoHS Versions Available
Total-AceXtreme Architectural Reference Guide. This document, which DDC can
provide under an NDA, includes detailed information about the Total-AceXtreme
architecture. This includes register bit maps and definitions, and detailed information
about the AceXtreme's data structures and operations for BC, Multi-RT, and Monitor
modes.
Data Device Corporation
www.ddc-web.com
® ®
, Linux , and VxWorks
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