DDC Total-AceXtreme MIL-STD-1553 Design Manual page 98

Table 12. Total-AceXtreme® PCI Interface Characteristics
PCI Characteristic/Feature
Target Burst Writes
Target Burst Reads
MSI Support
PRSNT[1::2]# Signals
CLKRUN Signal
PCI Power Management and PME# Signal
M66EN Signal
64-bit addressing
C/BE[7:4]
LOCK# Signal
The following describes the byte/word lane behavior for Total-AceXtreme® Memory
accesses:
6.5.1 PCI Memory Interface
• Writes to memory (BAR0) require either 2 high, 2 low, or all 4 byte lanes
(C/BE[3:0]) active or the writes will not take place (terminated on PCI bus and
discarded internally). This allows for either 16-bit or 32-bit writes to memory. 8-bit
memory writes are not supported.
• Reads from memory (BAR0) will ignore byte lanes because reads are non-
destructive and cause no state change to the circuit. This allows for any
combination of byte lane assertion to read a full 32-bit memory location.
6.5.2 PCI Register Interface
• Writes to registers (BAR1) require all 4 byte lanes to be active or the write will not
take place (terminated on PCI bus but discarded).
• Reads from registers (BAR1) require either 2 high, 2 low, or all 4 byte lanes active
and full 32-bit read will be returned over the PCI bus.
• Reads from registers (BAR1) without either 2 high, 2 low, or all 4 byte lanes active
will result in no read performed and 0's returned on the PCI bus.
• The PCI interface acts as a standard 32-bit PCI device. It can operate at 33 or
66MHz clock rates and will act as a bus master for DMA operations.
6.5.3 PCI Interface Diagram
Figure 48 shows the connection between a PCIbus and Total-AceXtreme®.
Data Device Corporation
www.ddc-web.com
H O S T I N T E R F A C E
Total-AceXtreme®
Supported to memory and registers
Supported only for Memory
NO
N/A
NO
NO
N/A
NO
NO
NO
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