Figure 37. Synchronous, Non-Multiplexed Address, 32-Bit - Sequential Burst Memory Read Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSS
nDATA_STRB
tAS
CPU_ADDR
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tLS
CPU_nLAST
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 37. Synchronous, Non-Multiplexed Address, 32-bit - Sequential Burst Memory
Figure 37 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) initiates the sequential burst transfer. nSELECT must be
asserted low through the full burst cycle.
2. The nDATA_RDY output is initially asserted low on the same clock cycle when
the Total-AceXtreme® drives the first valid data word on the data bus.
CPU_nLAST must be asserted high until the last word is to be read. On the
rising clock edge following CPU_nLAST asserting low, the last word is
removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted
(high). At this time (or later) nSELECT must be de-asserted high, completing
the burst read transfer.
3. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory word(s) are valid for this transfer. If either or both these bits is '0',
then the corresponding 16-bit word(s) will return a value of '0000'. These
inputs should be tied high if unused.
4. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tSH
tAH
Address
tAH
tDD
Data
tRDD
Read Transfer Timing
H O S T I N T E R F A C E
Data Data Data Data Data
77
tCH tSHC
tAH
tAH
tLS
tLH tLH
tDH
Data Data
tRDD
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