DDC Total-AceXtreme MIL-STD-1553 Design Manual page 134

BALL Signal Name
B12 GND_LOGIC
B13 GND_LOGIC
B14 GND_LOGIC
B15 NC
B16 NC
B17 NC
B18 NC
C1 NC
PCI_AD(25)/CPU_DATA(
C2 25)
C3 IRDY#/CPU_ADDR(07)
C4 +3.3V_LOGIC
C5 +3.3V_LOGIC
C6 +3.3V_LOGIC
C7 +3.3V_LOGIC
C8 +3.3V_LOGIC
C9 +3.3V_LOGIC
C10 nPOR
C11 PCI_nCPU
C12 +3.3V_LOGIC
C13 DISABLE_BIST
C14 DISABLE_BC
C15 NC
C16 NC
C17 NC
C18 NC
PCI_AD(26)/CPU_DATA(
D1 26)
D2 IDSEL/CPU_ADDR(10)
PCI_AD(24)/CPU_DATA(
D3 24)
D4 GND_LOGIC
D5 GND_LOGIC
D6 GND_LOGIC
D7 GND_LOGIC
D8 GND_LOGIC
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T O T A L - A C E X T R E M E ® S I G N A L S
Table 26. Signal Pinout by Ball Location
BALL Signal Name
H12 DISCRETE_IO_7
H13 RTADP
H14 RTAD4
H15 NC
H16 NC
H17 NC
H18 NC
J1 DEVSEL#/CPU_ADDR(09)
J2 SERR#
J3 TRDY#/CPU_ADDR(06)
J4 C/BE[2]#/CPU_ADDR(02)
J5 PCI_AD(17)/CPU_DATA(17)
J6 RD_nWR
J7 CPU_ASYNC_nSYNC
J8 RXDATA_IN_A
J9 RXDATA_IN_A_L
J10 TXDATA_OUT_A
J11 TXDATA_OUT_A_L
J12 DISCRETE_IO_5
J13 DISCRETE_IO_4
J14 GND_LOGIC
J15 NC
J16 NC
J17 NC
J18 NC
K1 PCI_AD(15)/CPU_DATA(15)
K2 PCI_AD(10)/CPU_DATA(10)
K3 PCI_AD(04)/CPU_DATA(04)
K4 PCI_AD(01)/CPU_DATA(01)
K5 C/BE[1]#/CPU_ADDR(01)
K6 DATA32_n16
K7 POL_SEL
K8 RXDATA_OUT_A
125
BALL Signal Name
P12 GND_XCVR
P13 TX_INH_A
P14 TX_INH_B
P15 NC
P16 NC
P17 CHB_1553 (I/O)
P18 CHB_1553 (I/O)
R1 nDATA_RDY
R2 MEM_nREG
R3 ADDR_LAT
R4 CPU_nLAST
R5 GND_XCVR
R6 GND_XCVR
R7 GND_XCVR
R8 GND_XCVR
R9 GND_XCVR
R10 NC
R11 GND_XCVR
R12 GND_XCVR
R13 nSINGEND
R14 nSSFLAG
R15 NC
R16 NC
R17 CHB_1553_L
R18 CHB_1553_L
T1 NC
T2 nSELECT
T3 CPU_ADDR(14)
T4 CPU_ADDR(15)
T5 +3.3V_XCVR
T6 +3.3V_XCVR
T7 +3.3V_XCVR
T8 +3.3V_XCVR
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