Figure 34. Synchronous, Multiplexed Address 16-Bit Single-Word Register Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSH
tSS
nDATA_STRB
tALH
tALS
ADDR_LAT
tAS
MSW_nLSW
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tAS tAH
MEM_nREG
tAS tAH
Address
CPU_DATA
nDATA_RDY
CPU_nSTOP
CPU_nLAST

Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing

Figure 34 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. For a register read access, CPU_nSTOP asserts (low) simultaneous with
nDATA_RDY, and de-asserts (high) on the host clock cycle following
nSELECT returning high.
Data Device Corporation
www.ddc-web.com
tWait
tCH
tOH
tDD tOHZ
Data A
tRDD tRDD
tSTPD tSTPD
H O S T I N T E R F A C E
tWait
tCS
tSH
tSS
tALH
tALS
tAS
tAS tAH
tAS tAH
Address
74
tCH tSHC
tAH
tAH
tAH
tOH
tDD tOHZ
Data B
tRDD tRDD
tRDD tRDD
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