Host Interface; Host Interface Configuration Options; Parallel Cpu Interface - DDC Total-AceXtreme MIL-STD-1553 Design Manual

6

HOST INTERFACE

6.1

Host Interface Configuration Options

The Total-AceXtreme® device has a highly flexible host interface. At top-level, the
Total-AceXtreme provides nine options for its host interface. Overall, the nine
options include:
• Asynchronous 32-bit with separate address and data buses
• Asynchronous 32-bit with multiplexed address and data bus
• Asynchronous 16-bit with separate address and data buses
• Asynchronous 16-bit with multiplexed address and data bus
• Synchronous 32-bit with separate address and data buses
• Synchronous 32-bit with multiplexed address and data bus
• Synchronous 16-bit with separate address and data buses
• Synchronous 16-bit with multiplexed address and data bus
• 32-bit Target/Initiator PCI interface
6.2

Parallel CPU Interface

The first eight options listed above are the modes for the Total-AceXtreme's parallel
CPU interface. As shown, the options for the parallel CPU interface are based on
three parameters: Asynchronous vs. Synchronous, 32-bit vs. 16-bit, and non-
multicast vs. multicast address and data buses.
In Asynchronous mode, the host processor does not provide a data transfer clock as
an input to the Total-AceXtreme. In this mode, all transfer timing is controlled by the
Total-AceXtreme's internal 160 MHz clock, which is derived from the Total-
AceXtreme's 40 MHz CLK_IN input. In Synchronous mode, the timing of transfers
between the host CPU and the Total-AceXtreme is controlled by a clock provided by
the host, and connected to the Total-AceXtreme's HOST_CLK input. The Total-
AceXtreme can operate with HOST_CLK speeds of up to 80 MHz. In addition for
Synchronous mode, certain aspects of the data transfers are controlled by the Total-
AceXtreme's internally derived 160 MHz clock.
In 32-bit mode, data is transferred over CPU_DATA(31:0). In 16-bit mode, data is
transferred over CPU_DATA(15:0), while CPU_DATA(31:16) aren't used.
In non-multiplexed mode, the host processor presents its address over the Total-
AceXtreme's address bus input, CPU_ADDR(15:0); that is on a separate path from
the data, which is transferred over CPU_DATA(31:0) or CPU_DATA(15:0). In
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