DDC Total-AceXtreme MIL-STD-1553 Design Manual page 107

1. Provide 1.8V power to the Total-AceXtreme's 1.8V_PLL and 1.8V_CORE pins.
Note that in order to ensure correct initialization, the PLL_+1.8V and
1.8V_CORE voltages must rise to ≥ 1.0 volts prior to or simultaneous with the
+3.3V_LOGIC and +3.3V_XCVR voltage rising to ≥ 2.0 volts.
2. Provide 3.3V power to the Total-AceXtreme's 3.3V_LOGIC and +3.3V_XCVR
pins. During the ramp-up of the +3.3V supply, external logic inputs must not be
driven to voltages above that of the Total-AceXtreme's 3.3V supply voltage. It
is acceptable to power external logic (including the oscillator for clock inputs)
from the same +3.3V supply voltage as the Total-AceXtreme.
3. When (or following) the 3.3V_LOGIC and +3.3V_XCVR voltages rise to above
2.0V, it will be necessary for the 40 MHz CLK_IN clock to be stable and to
assert the nPOR input to logic '0'. Asserting nPOR low is necessary to ensure
the correct initialization of the Total-AceXtreme.
4. Following a minimum of 1 µs after nPOR is low and CLK_IN is stable, the nPOR
input signal should be transitioned from '0' to '1'.
5. If enabled (i.e., if DISABLE_BIST = '0') the Total-AceXtreme will initiate its
internal built-in self-test (BIST) 100 µs after the low-to-high transition of nPOR.
6. The host processor or external PCI Initiator should not attempt to access the
Total-AceXtreme's memory and registers until at least 1 ms following the low-
to-high transition of nPOR if DISABLE_BIST = '0', or until at least 500 µs
following the low-to-high transition of nPOR if DISABLE_BIST = '1'.
The PLL_LOCKED output signal will assert high within 100 µs after the low-to-high
transition of nPOR, indicating that the internal 160 MHz clock (PLL output) is
operational. If this signal does not rise, the internal chip reset will remain in place
and the chip will be unresponsive.
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