11.4 Total-Acextreme® Pin Diagram; Figure 61. Total-Acextreme® Pin Diagram - DDC Total-AceXtreme MIL-STD-1553 Design Manual

11.4 Total-AceXtreme® Pin Diagram
A B C D
CHA_15
NC NC NC
18
53_L
CHA_15
NC NC NC
17
53_L
NC NC NC NC
16
GND_
NC NC NC
15
LOGIC
DISAB
GND_ GND_
DISAB
14 _MULT
LOGIC LOGIC
_BC
_RT
GND_
nRT
DISAB_B
PLL_LOC
13
LOGIC
KED IST BOOT
GND_ GND_ +3.3V
NC
12
LOGIC LOGIC LOGIC
GND_ GND_ GND_
PCI_nC
11
LOGIC LOGIC LOGIC
PU
+3.3V
JTAG JTAG
10
nPOR
LOGIC
TMS TDI
+3.3V GND_LO
PCI_INT JTAG
9
LOGIC GIC
A# nTRST
+3.3V GND_
JTAG
CLOCK_I
8
LOGIC LOGIC
N TDO
PCIREQ#/ +3.3V GND_
JTAG
7 CPU_ADD
LOGIC LOGIC
TCK
R(12)
+3.3V GND_
PCI_GNT#
RST#/
6 /CPU_AD
LOGIC LOGIC
nMSTCLR
DR (13)
+3.3V GND_
PCI_AD31/ PCI_AD29/
5
LOGIC LOGIC
DATA31 DATA29
+3.3V GND_
PCI_AD30/ PCI_AD28/
4
LOGIC LOGIC
DATA30 DATA28
PCI_IRDY
PCI_AD27/ PCI_AD24/
NC
3
#/CPU_AD
DATA27 DATA24
DR(7)
PCI_IDSE
PCI_AD25/
NC NC
2
L/CPU_AD
DATA25
DR(10)
PCI_AD26/
NC NC NC
1
DATA26
A B C D
PCI BUS
CPU BUS
Data Device Corporation
www.ddc-web.com
E
F G H
CHA_15 CHA_15 CHA_15
NC
53_L 53 53
CHA_15 CHA_15 CHA_15
NC
53_L 53 53
NC NC NC NC
NC NC NC NC
GND_ GND_
RTAD RTAD
LOGIC LOGIC
0 4
TEMP_ GND_
RTAD RTAD
DIODE LOGIC
1 P
GND_ GND_
RTAD DISC
XCVR XCVR
3 IO (7)
GND_ GND_
RT_AD
TXINH_
XCVR XCVR
IN_A
_LAT
GND_ GND_
RTAD
TXINH_
LOGIC LOGIC
2 OUT_A
GND_ GND_ GND_ +3.3V
LOGIC LOGIC LOGIC LOGIC
1.8V 1.8V GND_ +3.3V
PLL CORE LOGIC LOGIC
1.8V 1.8V GND_ +3.3V
CORE CORE LOGIC LOGIC
1.8V 1.8V GND_ +3.3V
CORE CORE LOGIC LOGIC
1.8V 1.8V GND_ +3.3V
CORE CORE LOGIC LOGIC
GND_ GND_ GND_ +3.3V
LOGIC LOGIC LOGIC LOGIC
PCI_FRA
PCI_AD21/ PCI_AD20/ PCI_AD18/
ME#/CPU_
DATA21 DATA20 DATA18
ADDR(5)
PCI_PERR PCI_STOP
HOST_
PCI_AD22/
#/CPU_AD #/CPU_AD
DATA22
CLK
DR(11) DR(8)
C/BE3#/C
PCI_AD23/ PCI_AD19/ PCI_AD16/
PU_ADDR
DATA23 DATA19 DATA16
(3)
E
F G H
MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM
1553 MISC
MISC
Figure 61. Total-AceXtreme® Pin Diagram
T O T A L - A C E X T R E M E ® S I G N A L S
J M
K L
NC NC NC NC
NC NC NC NC
NC NC NC NC
NC NC NC NC
GND_ GND_
DISC DISC
LOGIC LOGIC
IO (6) IO (0)
DISC DISC DISC TAG_
IO (4) IO (1) IO (3) CLK
DISC DISC TAG_LO
nMCRST/
nINCMD
IO (5) IO (2) AD
TXDATA
TXDATA TXINH_ TXINH
_OUT_A_
_IN_A_L OUT_B _IN_B
L
TXDATA TXDATA TXDATA TXDATA
_OUT_A _IN_A _OUT_B _IN_B
TXDATA
RXDATA TXDATA
RXDATA_
_OUT_B_
OUT_A_L
_IN_A_L _IN_B_L
L
TRIG_
RXDATA RXDATA
NC
_IN_A _OUT_A SEL
CPU_AS CPU_
+3.3V
POL_
YNC_nS AD_
LOGIC
SEL
YNC MULTI
RD_ DATA32 MSW_ nDATA_
nWR _n16 nLSW STRB
C/BE1#/C
PCI_AD17/ PCI_AD0/ PCI_AD3/
PU_ADDR
DATA17 DATA0 DATA3
(1)
C/BE2#/C
PCI_AD1/ PCI_AD2/ PCI_AD5/
PU_ADDR
DATA1 DATA2 DATA5
(2)
C/BE0#/
PCI_TRDY
PCI_AD4/ PCI_AD11/
CPU_A
#/CPU_AD
DATA4 DATA11
DR(6)
DDR(0)
PCI_PAR/
PCI_SE
PCI_AD10/ PCI_AD14/
CPU_ADD
DATA10 DATA14
RR#
R(4)
DEVSEL#/
PCI_AD15/ PCI_AD13/ PCI_AD9/
CPU_ADD
DATA15 DATA13 DATA9
R(9)
J M
K L
TEST / PROGRAM PAD
CONFIG PAD (STATIC)
128
P R T
N
CHB_15 CHB_15 CHB_15 CHB_15
53 53 53_L 53_L
CHB_15 CHB_15 CHB_15 CHB_15
53 53 53_L 53_L
NC NC NC NC
NC NC NC NC
IRIG_ TX_INH nSSFLA
NC
DIG_IN _B G
TAG_ TX_INH nSNGE USER_
ENABLE _A ND OUT_1
GND_ GND_
NC NC
XCVR XCVR
GND_ GND_
EXT_
NC
XCVR XCVR
TRIG
NC NC NC NC
+3.3V GND_ GND_ +3.3V
XCVR XCVR XCVR XCVR
+3.3V GND_ GND_ +3.3V
XCVR XCVR XCVR XCVR
+3.3V GND_ GND_ +3.3V
XCVR XCVR XCVR XCVR
+3.3V GND_ GND_ +3.3V
XCVR XCVR XCVR XCVR
+3.3V GND_ GND_ +3.3V
XCVR XCVR XCVR XCVR
CPU_W CPU_ CPU_A
PCI_AD6/
DATA6
DEN1 nBLAST DDR15
CPU_W ADDR_L CPU_A
PCI_AD7/
DATA7
DEN0 AT DDR14
MEM_ nSELEC
PCI_AD8/
nINT
DATA8
nREG T
CPU_ nDATA_
PCI_AD12/
NC
DATA12
nSTOP RDY
P R T
N
XCVR MISC
DS-BU-67301B-G
U V
NC NC
18
NC NC
17
NC NC
16
GND_
NC
15
LOGIC
GND_ GND_
14
LOGIC LOGIC
USER_
NC
13
OUT_2
NC NC
12
NC NC
11
+3.3V GND_
10
XCVR XCVR
NC NC
9
NC NC
8
RXDATA RXDATA_
7
_IN_B_L OUT_B_L
RXDATA RXDATA
6
_IN_B _OUT_B
NC NC
5
NC NC
4
NC NC
3
NC NC
2
NC NC
1
U V
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