DDC Total-AceXtreme MIL-STD-1553 Design Manual page 125

Signal Name
nDATA_RDY (O)
CPU_ASYNC_nSYNC (I)
ADMULTI (I)
CPU_nLAST (I)
CPU_WORD_EN(1) (I)
CPU_WORD_EN(0) (I)
CPU_nSTOP (O)
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Table 19. CPU Data Bus
BAL Pullup/
L Pulldown
R1 N/A Handshake output to host processor.
Active low signal indicating that a write transfer has been accepted or a read
transfer is ready on the data bus.
In asynchronous mode, nDATA_RDY will assert low when data to be read is
valid on the CPU_DATA bus, or when data to be written has been stored in
memory. In asynchronous mode, nDATA_RDY will remain asserted until
nDATA_STRB has been de-asserted.
In synchronous mode, nDATA_RDY will assert for a single cycle of the host
clock when data to be read is valid on the CPU_DATA bus, or when data to be
written has been stored in memory.
J7 50k Pullup Indicating ASYNCHRONOUS CPU mode when equal to '1' and
SYNCHRONOUS CPU mode when equal to '0'.
L7 50k Pullup When '0' indicates non-multiplexed mode, when '1' indicates multiplexed
address and data mode.
R4 50k Pullup In synchronous mode, when asserted to '1', CPU_nLAST enables a burst
transfer. When de-asserted to '0', this indicates the last transfer of a burst or a
single read or write transfer. CPU_nLAST should be active through the entire
transfer cycle.
Not used in asynchronous mode.
P4 50k Pullup Signal(s) should be active throughout the entire transfer cycle.
32-Bit Mode:
Input to specify which input 16-bit data words are valid for this transfer.
Should be tied high if unused. For valid register transfers the value should be
'11' always. For memory accesses, these bits indicate which word(s) will be
P3 50k Pullup
written/read.
16-Bit Mode: (only CPU_WORD_EN(0) used):
In 16-bit mode, CPU_WORD_EN[1:0] must be connected to '11'.
P1 N/A For synchronous mode, CPU_nSTOP is issued by the CPU Target Interface
to direct the Host Interface to immediately terminate the current transaction.
If CPU_nSTOP is coincident with nDATA_RDY, then the final transaction is
acceptable. If CPU_nSTOP is not coincident with nDATA_RDY, then the
transaction should be aborted.
CPU_nSTOP will be asserted at the completion of a single register read cycle
and is coincident with nDATA_RDY. CPU_nSTOP should not be expected at
the completion of a valid single memory read cycle, or any valid single write
cycle, because the Total-AceXtreme target interface is not yet certain whether
this is a burst cycle or not. In addition, CPU_nSTOP will go active low when
the target determines a transfer did not complete (i.e. a FIFO is full or an
invalid transfer). When asserted, the next transfer shall not start until at least
one clock after CPU_nSTOP has been de-asserted.
CPU_nSTOP is not used in asynchronous mode.
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