Register And Memory Addressing; 10.1 Memory Address Space; 10.2 Register Address Space - DDC Total-AceXtreme MIL-STD-1553 Design Manual

10

REGISTER AND MEMORY ADDRESSING

10.1 Memory Address Space

The Total-AceXtreme's memory and registers are accessible from either the PCI
Interface or the CPU Interface.
When using the PCI Interface, the Total-AceXtreme® memory is accessed from
BAR0 via byte addresses on the PCI bus. On the BC/RT/MT versions, the BAR0 size
is 256KByte.
When using the CPU Interface, the Total-AceXtreme memory is accessed via 32-bit
transactions addresses on the CPU bus. The entire memory range (256 KBytes) is
accessible through the Host interface.

10.2 Register Address Space

Total-AceXtreme® registers are accessible from both the PCI Interface and CPU
Interface.
When using the PCI Interface, the Total-AceXtreme registers are accessed from
BAR1 via byte addresses on the PCI bus. BAR1 is always 4Kbytes in size
regardless of the Total-AceXtreme's mode of operation.
When using the CPU interface, the Total-AceXtreme registers are accessed via 32-
bit addresses on the CPU bus. Any attempt to read/write a register location beyond
address x"3FF" will result in a rollover back to the beginning of the 4Kbyte space.
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