Table 6. Asynchronous Transfers; Table 7. Asynchronous Timing Information - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Asynchronous Timing Information
Table 6 lists the eight Asynchronous mode timing diagrams, Figure 11 through Figure
18, while Table 7 lists the timing parameters that are applicable for these diagrams.
Non-Multiplexed or
Multiplexed
Address/Data
Non-Multiplexed
Non-Multiplexed
Non-Multiplexed
Non-Multiplexed
Multiplexed
Multiplexed
Multiplexed
Multiplexed
REF
t nSELECT setup time prior to nDATA_STRB low (for non-
SS
multiplexed address) or ADDR_LAT high (for multiplexed
address)
t nSELECT hold time following nDATA_STRB high
SH
t CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN
AS
valid setup time prior to nDATA_STRB low (for non-multiplexed
address) or ADDR_LAT high (for multiplexed address)
t CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN
AH
valid hold time following nDATA_STRB high (for non-multiplexed
address) or ADDR_LAT low (for multiplexed address)
t Maximum delay from nDATA_STRB falling edge to nDATA_RDY
Wait
falling edge
(32-bit read or
first 16-bit read)
t Maximum delay from nDATA_STRB falling edge to nDATA_RDY
Wait
falling edge
(second 16-bit
read)
t Maximum delay from nDATA_STRB falling edge to nDATA_RDY
Wait
falling edge
(write)
t During READ operations: CPU_DATA valid delay following falling
DD
Data Device Corporation
www.ddc-web.com

Table 6. Asynchronous Transfers

32-bit or 16-bit
32
32
16
16
32
32
16
16

Table 7. Asynchronous Timing Information

DESCRIPTION
H O S T I N T E R F A C E
Read or Write Timing Diagram
Read
Write
Read
Write
Read
Write
Read
Write
NOTES
10pF load
41
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Timing
Characteristics
UNITS
MIN TYP MAX
0
0
10
7
70
40
40
5
DS-BU-67301B-G
1/14
ns
ns
ns
ns
ns
ns
ns
ns