Pci Interface; Table 12. Total-Acextreme® Pci Interface Characteristics - DDC Total-AceXtreme MIL-STD-1553 Design Manual

6.5

PCI Interface

In addition to the flexible parallel CPU interface, the Total-AceXtreme® also includes
a PCI 2.3 compliant Target/Initiator interface. Table 12 lists the features and
characteristics of the Total-AceXtreme's PCI interface.
Table 12. Total-AceXtreme® PCI Interface Characteristics
PCI Characteristic/Feature
PCI Specification Compliance
Maximum PCI clock frequency
Support 32-bit PCI Bus
Support 64-bit PCI Bus (AD[63::32])
3.3V Signaling
5V Tolerant
PCI Target Interface
PCI Initiator Interface
Single-Channel PCI Initiator/DMA Engine
PCI Initiator/DMA Engine: Transfer Directions
PCI Initiator/DMA Engine: Data Transfer Modes
PCI Initiator/DMA Engine: PCI burst lengths
PCI Initiator/DMA Engine: PCI Retry timeout
PCI Initiator/DMA Engine: Programmable Interrupts
Memory and Register Addressability
Interrupts supported
PCI Retries
Disconnect with Data
Target Abort
Delayed Transactions
BAR0/BAR1 Support
Zero wait state bursts
Data Device Corporation
www.ddc-web.com
H O S T I N T E R F A C E
Total-AceXtreme®
Revision 2.3
66 MHz
YES
NO
YES
NO
YES
YES
Memory only, not registers
Supports transfers in both directions: host-to-Total-
AceXtreme and Total-AceXtreme -to-host.
•
Block transfer mode (single descriptor execution
via registers).
•
Scatter/gather mode (descriptors stored in host
memory)
Programmable (including infinite)
Programmable (including infinite)
•
DMA Complete
•
DMA Descriptor Done
•
DMA Abort Function via register control
•
DWord or Word write accesses to memory
•
DWord write accesses to registers
•
DWord or Word read accesses from registers
•
No 8-bit accesses
INTA#
Supported
Supported
Total-AceXtreme will never generate a target abort
Supports up to two simultaneous
BAR0 = Total-AceXtreme Memory
BAR1 = Total-AceXtreme Registers
Supported, for both reads and writes as both Target
and Initiator
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