Table 5. Asynchronous 16-Bit Mode Configuration Options - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Table 5. Asynchronous 16-bit Mode Configuration Options

TRIG_SEL POL_SEL
1
1
1
1
0
0
0
0
6.3.1.2 Asynchronous Mode Connection Diagrams
Figure 7 through Figure 10 show the four possible Asynchronous mode interface
configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and
multiplexed.
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RD_nWR
MSW_nLSW = 0
1 1
CPU  RAM 31:16
MSW_nLSW = 0
1 0
CPU  RAM 31:16
MSW_nLSW = 1
0 1
CPU  RAM 31:16
MSW_nLSW = 1
0 0
CPU  RAM 31:16
MSW_nLSW = 1
1 1
CPU  RAM 15:0
MSW_nLSW = 1
1 0
CPU  RAM 15:0
MSW_nLSW = 0
0 1
CPU  RAM 15:0
MSW_nLSW = 0
0 0
CPU  RAM 15:0
H O S T I N T E R F A C E
FIRST WORD
TRANSFER
MSW_nLSW = 1
CPU  RAM 15:0
MSW_nLSW = 1
CPU  RAM 15:0
MSW_nLSW = 0
CPU  RAM 15:0
MSW_nLSW = 0
CPU  RAM 15:0
MSW_nLSW = 0
CPU  Buffer 31:16
MSW_nLSW = 0
CPU  RAM 31:16
MSW_nLSW = 1
CPU  RAM 31:16
MSW_nLSW = 1
CPU  RAM 31:16
36
SECOND WORD
TRANSFER
DS-BU-67301B-G
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