DDC Total-AceXtreme MIL-STD-1553 Design Manual page 19

Table 1. Total-AceXtreme® Series Specifications
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• Logic +3.3V (V )
DDIO
• Logic +3.3V (V ) Ramp Rate
DDIO
• Core and PLL +1.8V (V
CORE
• Core and PLL +1.8V (V
CORE
• Transceivers +3.3V
Current Drain (Total Hybrid) (Note 10)
3.3V (I/O and transceiver) (Note 10):
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
1.8V (logic core) (Note 10)
POWER DISSIPATION: TOTAL HYBRID (Note 10)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
POWER DISSIPATION: TRANSCEIVER CHIP (Note 10)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
CLOCK INPUTS
PCI CLOCK INPUT FREQUENCY
HOST_CLK (CPU) CLOCK INPUT FREQUENCY
CLOCK_IN (MIL-STD-1553) FREQUENCY
• Nominal Value
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
Duty Cycle
Jitter Tolerance
Data Device Corporation
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and V )
PLL
and V ) Ramp Rate
PLL
MIN TYP
3.0 3.3
1.65 1.8
3.135 3.3
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
0 —
0 —
— 40
0.01 —
0.10 —
—
-0.001
—
-0.01
—
40
—
—
10
O V E R V I E W
MAX UNITS
3.6 V
1.85 V/µs
1.95 V
1.85 V/µs
3.465 V
40 mA
214 mA
344 mA
624 mA
160 mA
0.42 W
0.58 W
0.70 W
0.90 W
0.09 W
0.23 W
0.33 W
0.50 W
66 MHz
80 MHz
— MHz
-0.01 %
-0.10 %
0.001 %
0.01 %
60 %
100 Ps
DS-BU-67301B-G
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