Table 4. Summary Of The Operation Of The Ndata_Rdy Output Signal For Synchronous Single-Word Memory And Register Accesses - DDC Total-AceXtreme MIL-STD-1553 Design Manual

The operation of the nDATA_RDY signal for single-word Synchronous memory
and register accesses is summarized in Table 4 and described in the paragraphs
that follow.
Table 4. Summary of the Operation of the nDATA_RDY Output Signal for
Transfer Type
32-bit Read
32-bit Write
16-bit Read: First Word
16-bit Read: Second Word
16-bit Write: First Word
16-bit Write: Second Word
For 32-bit Synchronous single-word memory read accesses, nDATA_RDY
asserts low when the Total-AceXtreme® drives valid data to be read on
CPU_DATA(31:0), and de-asserts high on the HOST_CLK rising edge after
nSELECT is sampled high.
For Synchronous 32-bit single-word memory or register write accesses,
nDATA_RDY asserts low for a single host clock cycle when the data from
CPU_DATA(31:0) has been internally latched.
For Synchronous single-word register read accesses, nDATA_RDY asserts low
for a single host clock cycle beginning when the Total-AceXtreme® drives valid
data to be read on CPU_DATA(31:0) for a 32-bit transfer, or CPU_DATA(15:0)
for each of the two 16-bit transfers.
For each of the two transfers for 16-bit Synchronous single-word memory read
accesses, nDATA_RDY asserts low starting when the Total-AceXtreme® drives
valid data to be read on CPU_DATA(15:0) and de-asserts high on the
HOST_CLK rising edge after nSELECT is sampled high.
For each of the two transfers for 16-bit Synchronous single-word memory write
accesses, nDATA_RDY asserts low for a single host clock cycle when the Total-
AceXtreme® internally latches the data transferred over CPU_DATA(15:0).
Data Device Corporation
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Synchronous Single-Word Memory and Register Accesses
Operation of nDATA_RDY
Asserts low until host clock
following nSELECT going high
Asserts low for single clock cycle
Asserts low until host clock
following nSELECT going high
Asserts low until host clock
following nSELECT going high
Asserts low for single clock cycle
Asserts low for single clock cycle
H O S T I N T E R F A C E
for Memory Access
33
Operation of nDATA_RDY
for Register Access
Asserts low for single clock cycle
Asserts low for single clock cycle
Asserts low for single clock cycle
Asserts low for single clock cycle
Asserts low until host clock
following nSELECT going high.
Asserts low for single clock cycle
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