Figure 41. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSS
nDATA_STRB
tAS
CPU_ADDR
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
CPU_nLAST
tAS
MSW_nLSW
tDS
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 41. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Write
Figure 41 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) and valid address presented initiates the sequential burst write
transfer. nSELECT must be asserted low through the full burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the Total-AceXtreme® reads the first 16-bit data word from the
data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be
written. On the rising clock edge following CPU_nLAST asserting low, the
Total-AceXtreme reads the last 16-bit word from the data bus, and
nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be
de-asserted high, completing the burst write transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tSH
tAH
Address
tAH
tLS
tAH
tDH
Data Data
tRDD
Transfer Timing
Data Data Data Data Data Data
81
H O S T I N T E R F A C E
tCH tSHC
tAH
tAH
tLS
tLH tLH
tAH
tDH
Data Data
tRDD
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