DDC Total-AceXtreme MIL-STD-1553 Design Manual page 7

Figure 1. BU-67301B Total-AceXtreme® ..................................................................................6
Figure 2. Total-AceXtreme® Block Diagram ..............................................................................7
Figure 3. Bus Controller Block Diagram - Remote Terminal Operation ................................... 16
Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation .................................... 18
Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH) ......................................... 19
Figure 6. PCI DMA Block Diagram - Digital I/O ....................................................................... 23
Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface ....................................... 37
Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface ............................................... 38
Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface ....................................... 39
Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface ............................................. 40
Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing ................................. 43
Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing ................................. 44
Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing ................................. 45
Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing ................................. 46
Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing ........................................ 47
Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing ......................................... 48
Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing ........................................ 49
Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing ......................................... 50
Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface ....................................... 56
Figure 20. 32-bit, Multiplexed Address, Synchronous Interface .............................................. 57
Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface ....................................... 58
Figure 22. 16-bit, Multiplexed Address, Synchronous Interface .............................................. 59
Figure 23. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Memory Read Timing
.......................................................................................................................................... 63
Figure 24. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Register Read Timing
.......................................................................................................................................... 64
Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write Timing ........... 65
Figure 26. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Memory Read Timing
.......................................................................................................................................... 66
Figure 27. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Register Read Timing
.......................................................................................................................................... 67
Figure 28. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Memory Write Timing
.......................................................................................................................................... 68
Figure 29. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Register Write Timing
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Figure 30. Synchronous, Multiplexed Address 32-bit - Single-Word Memory Read Timing .... 70
Figure 31. Synchronous, Multiplexed Address 32-bit - Single-Word Register Read Timing .... 71
Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing ..................... 72
Figure 33. Synchronous, Multiplexed Address 16-bit - Single-Word Memory Read Timing .... 73
Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing ...... 74
Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing ....... 75
Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing ...... 76
Figure 37. Synchronous, Non-Multiplexed Address, 32-bit - Sequential Burst Memory Read
Transfer Timing ................................................................................................................. 77
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