DDC Total-AceXtreme MIL-STD-1553 Design Manual page 30

Following the issuance of ADH interrupts, the host can then transfer data from its
ADH memory to designated areas in host space or PCI space memory. These
transfers may be performed over either the parallel CPU or PCI Target interfaces, or
by means of the Total-AceXtreme's DMA engine and PCI Initiator interface.
Data Device Corporation
www.ddc-web.com
M I L - S T D - 1 5 5 3 M O D E S A N D A R C H I T E C T U R E
21
DS-BU-67301B-G
1/14