DDC Total-AceXtreme MIL-STD-1553 Design Manual page 41

• In 32-bit mode, CPU_WORD_EN(1) is used to activate memory transfers
for data bits 31 through 16, while CPU_WORD_EN(0) is used to activate
memory transfers for data bits 15 through 0. In 32-bit mode, these two
inputs are used to specify which 16-bit data memory word(s) are valid for a
memory transfer.
• For a 32-bit memory write transfer, if either or both of the
CPU_WORD_EN(1:0) inputs is '0', then the respective 16-bit word(s) will
not be written to Total-AceXtreme® memory.
• For a 32-bit memory read transfer, if either or both of the
CPU_WORD_EN(1:0) inputs is '0', then the value of the respective 16-bit
word(s) returned that will be '0000'.
• For all register transfers, the value of CPU_WORD_EN(1:0) must always
be '11'.
• For 16-bit mode, CPU_WORD_EN(1:0) are not used and must be
connected to '11'.
• CPU_WORD_EN(1:0) should be tied to '11' if not used.
• HOST_CLK:
For the Synchronous interface mode, HOST_CLK is used for clocking address,
data, and control issues, and for generating the nDATA_RDY, nINT, and
CPU_nSTOP outputs. The maximum frequency for HOST_CLK is 80 MHz.
HOST_CLK is not used in the Asynchronous CPU mode, and may be left
unconnected.
6.2.2.3 Output Signals
• nDATA_RDY:
This active low signal is the main output control signal for the Total-AceXtreme's
CPU interface. Its specific operation varies as a function of Asynchronous vs.
Synchronous mode. In addition, for Synchronous mode, its function varies as a
function of single-word transfers vs. burst transfers.
For Asynchronous read transfers, nDATA_RDY asserts low when the Total-
AceXtreme drives valid data on to CPU_DATA(31:0) or CPU_DATA(15:0). For
Asynchronous write transfers, nDATA_RDY asserts low when the Total-
AceXtreme has latched data driven by the host over CPU_DATA(31:0),
CPU_DATA(31:16), or CPU_DATA(15:0). In either case, nDATA_RDY will
continue to assert low until the host de-asserts nSELECT high.
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