Table 11. Synchronous Timing Parameters - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Non-Multiplexed or
Multiplexed
Non-Multiplexed
Multiplexed
Multiplexed
Multiplexed
Multiplexed
Multiplexed 32-bit or 16-bit
Non-Multiplexed or 32-bit or 16-bit
Multiplexed
Non-Multiplexed or 32-bit or 16-bit
Multiplexed
REF
f HOST_CLK frequency
CLK
t HOST_CLK cycle time
CLK
t nDATA_STRB setup time (NOTE)
SS
t nDATA_STRB hold time (NOTE)
SH
t nSELECT setup time (NOTE)
CS
t nSELECT hold time (NOTE)
CH
t CPU_ADDR valid setup time (NOTE)
AS
t CPU_ADDR valid hold time (NOTE)
AH
t MSW_nLSW setup time (NOTE)
MS
t MSW_nLSW hold time (NOTE)
MH
t Read cycle latency from nDATA_STRB falling edge to
WAIT-READ
nDATA_RDY falling edge
t Write cycle latency from nDATA_STRB falling edge to
WAIT-
nDATA_RDY falling edge
WRITE
t CPU_DATA valid delay (NOTE)
DD
t nDATA_RDY delay (NOTE)
RDD
t CPU_DATA output valid hold time (NOTE)
OH
t CPU_DATA delay to high-Z (NOTE)
OHZ
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Table 10. Synchronous Burst Transfers
32-bit or Sequential
or Random
16-bit
16 Random
32 Sequential
32 Sequential
16 Sequential
16 Sequential
Random
Sequential or
Random
Random

Table 11. Synchronous Timing Parameters

DESCRIPTION
H O S T I N T E R F A C E
Register or Read or
Memory
Write
Memory or
Register
Memory
Memory or
Register
Memory
Memory or
Register
Memory or Read or Write
Register
Register
Memory or
Register
Timing Characteristics
NOTES
MIN
0
12.5
4
0
4
0
4
0
4
0
(6•t ) +
CLK
50
10pF load
10pF load 2
10pF load 2
10pF load
61
Timing Diagram
Write Figure 42
Read Figure 43
Write Figure 44
Read Figure 45
Write Figure 46
Not Supported
Read Not Supported
Read Not Supported
UNITS
TYP MAX
80
(7•t ) +
CLK
75
4•t
CLK
8
7
8
DS-BU-67301B-G
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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