DDC Total-AceXtreme MIL-STD-1553 Design Manual page 4

Revision Date
Pre Rev A Sept., 2010
Rev. A Sept., 2011
Rev. B Dec., 2011
Rev. C Dec., 2011
Rev. D January, 2012
Rev. E Feb., 2012
Rev. F June, 2012
Rev. G January, 2014
Data Device Corporation
www.ddc-web.com
Pages
All Preliminary release
All Initial Release
Table 1: removed part numbers from Supply Voltage
section, changed Storage Temperature Max. from:
+150°C to: +125°C., added Ramp Rate specs, added
Junction Temperature (T
6, 7, 9, 38, 113,
Table 7: Changed T
25-93, 95, 101-
Table 25: removed redundant B1 listing in NC section.
115
Section 6: changed heading to Host Interface.
Added Section 7: Power Inputs
Tables 15 - 22: Added Pullup/Pulldown column and
values
Table 1: Eliminated reference to "(Hottest Die)".
Figure 5: Eliminated "MT 100 µs Timer (16-bit)" block.
Added Figure 56, Timing of CLK_IN, Logic_V
10, 15, 96-97, 99, PLL_+1.8V, and Core_+1.8V.
100, 115
Figure 58: Made corrections
Figure 59: Made corrections
Table 22: Changed second column signal description
for nSINGEND(I).
Figure 2: Added nPOR and PLL_LOCKED
Figures 7-10 and Figures 19-22: Added nPOR,
supervisor circuit, and PLL_LOCKED, modifed use of
nMSTCLR
Figure 48: Added nPOR and PLL_LOCKED
7, 36-39, 55-58,
Paragraph 7.2: updated power-up sequence, modified
89. 96-98, 104,
Figure 56
107-108, 110,
122, 125
Table 15: Added nPOR and PLL_LOCKED
Table 18: Modified RST#
Table 19: Modified nMSTCLR
Table 26: Added nPOR and PLL_LOCKED
Figure 61: Added nPOR and PLL_LOCKED
98 Updated Figure 56
Figure 2: Corrected CH. A 1553 Stub designation
7, 104, 105
Tables 15 – 17: Adjusted column widths
11, 89 Updated Table 1 and Figure 48
ii
R E C O R D O F C H A N G E
Description
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min from 2ns to 7ns.
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DS-BU-67301B-G
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