Figure 52. Pci Dma Start Delay; Figure 53. Pci Dma Burst Write - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
REQ#
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
tCLK
HOST_CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
Data Device Corporation
www.ddc-web.com
Address
0x7

Figure 52. PCI DMA Start Delay

Address
0x7

Figure 53. PCI DMA Burst Write

H O S T I N T E R F A C E
Data
0x0
Data Data
0x0
95
t
DMA_Start
Data Data
DS-BU-67301B-G
1/14