Figure 30. Synchronous, Multiplexed Address 32-Bit - Single-Word Memory Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
nDATA_STRB
tALS
ADDR_LAT
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tAS
Address
CPU_DATA
nDATA_RDY
CPU_nSTOP
CPU_nLAST
Figure 30. Synchronous, Multiplexed Address 32-bit - Single-Word Memory Read
Figure 30 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory words are to be read for this transfer. If either or both these bits is '0',
then the corresponding 16-bit word(s) will return a value of '0000'. These
inputs should be tied high if unused.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for memory accesses, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tSH
tSS
tALH
tAH
tAH
Timing
H O S T I N T E R F A C E
tAH
tAH
tDD
Data
tRDD
70
tCH tSHC
tOH
tOHZ
tRDD
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