Table 16. Jtag Test; Table 17. General Purpose Discrete I/O - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Signal Name BALL
JTAG_TCK (I)
JTAG_TMS (I)
JTAG_TDI (I)
JTAG_TDO (O)
JTAG_nTRST (I)
Signal Name BALL
DISCRETE_IO_7 (I/O) H12
DISCRETE_IO_6 (I/O)
DISCRETE_IO_5 (I/O)
DISCRETE_IO_4 (I/O)
DISCRETE_IO_3 (I/O)
DISCRETE_IO_2 (I/O)
DISCRETE_IO_1 (I/O)
DISCRETE_IO_0 (I/O) M14
Data Device Corporation
www.ddc-web.com

Table 16. JTAG Test

Pullup/
Pulldown
A7 50k Pullup This ball is the JTAG test clock.
The Test Clock is used to load the test mode data from the JTAG TMS pin,
and the test data on the TDI pin [on the rising edge]. On the falling edge test
clock outputs the test data on the TDO pin.
A10 50k Pullup This ball is the test mode select input signal. Controls the operation of the
test logic, by receiving the incoming data.
B10 50k Pullup This ball is the serial test data input. Receives serial input data which is either
fed to the test data registers or instruction register.
B8 N/A This ball is the serial test data output. Outputs serial data which comes from
either the test data registers or instruction register.
B9 50k Pullup This ball is test reset and will asynchronously reset the JTAG test logic.

Table 17. General Purpose Discrete I/O

Pullup/
Pulldown
50k Pullup Discrete I/O (Digital Logic levels)
L14 50k Pullup
Following power-up, each register is reset to zero, and all outputs are reset to
J12 50k Pullup
high impedance state (input mode). All registers are read/write. Each
Discrete IO bit is independently programmable for input vs. output, and each
J13 50k Pullup
bit has independent 3-state control.
L13 50k Pullup
K12 50k Pullup
K13 50k Pullup
50k Pullup
T O T A L - A C E X T R E M E ® S I G N A L S
Description
Description
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