Figure 47. Timing For Assertion Of Cpu_Nstop - Output During Synchronous Burst Write Transfer - DDC Total-AceXtreme MIL-STD-1553 Design Manual

HOST_CLK
nSELECT
nDATA_STRB
CPU_ADDR
MEM_nREG
RD_nWR
CPU_WORD_EN[1:0]
CPU_nLAST
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 47. Timing for Assertion of CPU_nSTOP - Output During Synchronous Burst
Figure 47 Note:
In this example, the fourth word written by the host results in the filling of the Total-
AceXtreme®'s command FIFO to its capacity. The capacity of the command FIFO is
software programmable for either 32, 16, or 8 words. As a result, the Total-
AceXtreme will not be able to accept any further additional word transfers until one or
more commands are drained from the FIFO. At this time, the Total-AceXtreme will
terminate the current transfer by asserting its CPU_nSTOP output low.
If this occurs, it is recommended for the host to delay before attempting to retry the
current multi-word transfer. To ensure that the FIFO has drained sufficiently, the host
should delay for sufficient time to allow at least half of the words in the FIFO to be
drained. Assuming that the FIFO is fully populated with register write transfer
commands, these require 25 ns each to drain. Therefore, the minimum delay times to
prevent a subsequent "STOP" condition are 425 ns for a 32-word command FIFO;
225 ns for a 16-word command FIFO; and 125 ns for an 8-word command FIFO.
Data Device Corporation
www.ddc-web.com
tCLK tWait
tCS
tSH
tSS
tAH
tAS
Address
tAH
tAS
tAS
tAS
tLS
tDS
Data
Write Transfer
87
H O S T I N T E R F A C E
Last Valid Data
tDH tDH
Data Data Data Data
tRDD tRDD
tSTPD
tCH tSHC
tAH
tAH
Data
tLH
tSTPD
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